15

0h

RO

PME Status (PMESTS)

This bit is hardwired to 0 to indicate that IGD does not support PME# generation from D3 (cold).

14:13

0h

RO

Data Scale (DSCALE)

This field is hardwired to 00 to indicate IGD does not support data register.

12:9

0h

RO

Data Select (DSEL)

This field is hardwired to 0h to indicate IGD does not support data register.

8

0h

RO

PME Enable (PMEEN)

This bit is hardwired to 0 to indicate that PME# assertion from D3 (cold) is disabled.

7:4

0h

RO

Reserved

3

1h

RO

NO SOFT RESET (No_​Soft_​Reset)

When set (1), this bit indicates that devices transitioning from D3hot to D0 because of PowerState commands do not perform an internal reset. Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state, no additional operating system intervention is required to preserve Configuration Context beyond writing the PowerState bits.
When clear (0), devices do perform an internal reset upon transitioning from D3hot to D0 via software control of the PowerState bits. Configuration Context is lost when performing the soft reset. Upon transition from the D3hot to the D0 state, full reinitialization sequence is needed to return the device to D0 Initialized. Regardless of this bit, devices that transition from D3hot to D0 by a system or bus segment reset will return to the device state D0 Uninitialized with only PME context preserved if PME is supported and enabled.

2

0h

RO

Reserved

1:0

0h

RW

Power State (PWRSTAT)

This field indicates the current power state of the IGD and can be used to set the IGD into a new power state.
If software attempts to write an unsupported state to this field, write operation must complete normally on the bus, but the data is discarded and no state change occurs.
Behavior of the graphics controller in supported states is detailed in the power management section of the Bspec.
Bits[1:0] Power state:
00: D0 (Default)
01: D1 (Not Supported)
10: D2 (Not Supported)
11: D3