Intel® Core™ Ultra 200V Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 831649 | 03/30/2026 | 001 | Public |
PMON Global Status Register (NcuPmonGlobalStatus) – Offset e4b708
Performance Monitor Global Status Register
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 63:5 | 0h | RO | Reserved |
| 4 | 0h | RW/1C/V | HBO1 Counter Overflow (hbo1_ov) If an overflow is detected from hbo1 counters, the overflow bit will be set. |
| 3 | 0h | RW/1C/V | HBO0 Counter Overflow (hbo0_ov) If an overflow is detected from hbo0 counters, the overflow bit will be set. |
| 2 | 0h | RW/1C/V | MC1 Counter Overflow (mc1_ov) If an overflow is detected from mc1 counters, the overflow bit will be set. |
| 1 | 0h | RW/1C/V | MC0 Counter Overflow (mc0_ov) If an overflow is detected from mc0 counters, the overflow bit will be set. |
| 0 | 0h | RW/1C/V | sNCU Counter Overflow (sncu_ov) If an overflow is detected from sncu counters, the overflow bit will be set. |