Intel® Core™ Ultra 200V Series Processors CFG and MEM Registers

ID Date Version Classification
831649 03/30/2026 001 Public
Document Table of Contents
Document Table of Contents
Introduction Processor Configuration Register Definitions and Address Ranges D0:F0 Host Bridge and DRAM Controller - GTTMMADR D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1) D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1) D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3) D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4) D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management D0:F0 Host Bridge and DRAM Controller - SAFBAR PMON Registers Part1 D0:F0 Host Bridge and DRAM Controller - SAFBAR PMON Registers Part2 D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR D10:F0 Platform Monitoring Technology (PMT) Registers D11:F0 Vision Processing Unit D2:F0 Processor Graphics D4:F0 Dynamic Tuning Technology D5:F0 Image Processing Unit
Introduction
Processor Configuration Register Definitions and Address Ranges
D0:F0 Host Bridge and DRAM Controller - GTTMMADR
D0:F0 Host Bridge and DRAM Controller - GTTMMADR GT PState CAP (GT_PSTATE_CAP_0_2_0_GTTMMADR) (MEDIA_IA_PERF_BIAS_0_2_0_GTTMMADR) Package energy status (PACKAGE_ENERGY_STATUS_0_2_0_GTTMMADR) Package power sku unit (PACKAGE_POWER_SKU_UNIT_0_2_0_GTTMMADR) P-State Limits (P_STATE_LIMITS_0_2_0_GTTMMADR) Plane Turbo Performance BIAS (GT_IA_PERF_BIAS_0_2_0_GTTMMADR)
GT PState CAP (GT_PSTATE_CAP_0_2_0_GTTMMADR)
(MEDIA_IA_PERF_BIAS_0_2_0_GTTMMADR)
Package energy status (PACKAGE_ENERGY_STATUS_0_2_0_GTTMMADR)
Package power sku unit (PACKAGE_POWER_SKU_UNIT_0_2_0_GTTMMADR)
P-State Limits (P_STATE_LIMITS_0_2_0_GTTMMADR)
Plane Turbo Performance BIAS (GT_IA_PERF_BIAS_0_2_0_GTTMMADR)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1) Vendor ID (VID_0_0_0_PCI) Device ID (DID_0_0_0_PCI) PCI Command (PCICMD_0_0_0_PCI) PCI Status (PCISTS_0_0_0_PCI) Revision ID (RID_0_0_0_PCI) Class Code Programming Interface (CC_PI_0_0_0_PCI) Basic Class Code (CC_BCC_0_0_0_PCI) Header Type (HDR_0_0_0_PCI) Subsystem Vendor Identification (SVID_0_0_0_PCI) Subsystem Identification (SID_0_0_0_PCI) Capabilities Pointer (CAPPTR_0_0_0_PCI)
Vendor ID (VID_0_0_0_PCI)
Device ID (DID_0_0_0_PCI)
PCI Command (PCICMD_0_0_0_PCI)
PCI Status (PCISTS_0_0_0_PCI)
Revision ID (RID_0_0_0_PCI)
Class Code Programming Interface (CC_PI_0_0_0_PCI)
Basic Class Code (CC_BCC_0_0_0_PCI)
Header Type (HDR_0_0_0_PCI)
Subsystem Vendor Identification (SVID_0_0_0_PCI)
Subsystem Identification (SID_0_0_0_PCI)
Capabilities Pointer (CAPPTR_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2) MCHBAR Base Address Register (MCHBAR_0_0_0_PCI) Graphics Control (GGC_0_0_0_PCI) Device Enable (DEVEN_0_0_0_PCI) Protected Audio Video Path Control (PAVPC_0_0_0_PCI) DMA Protected Range (DPR_0_0_0_PCI) PCIEXBAR Base Address Register (PCIEXBAR_0_0_0_PCI) SAFBAR PCI (SAFBAR_0_0_0_PCI) CAPID_DEV_CDIE PCI (CAPID_DEV_CDIE_0_0_0_PCI) Programmable Attribute Map 0 (PAM0_0_0_0_PCI) Programmable Attribute Map 1 (PAM1_0_0_0_PCI) Programmable Attribute Map 2 (PAM2_0_0_0_PCI) Programmable Attribute Map 3 (PAM3_0_0_0_PCI) Programmable Attribute Map 4 (PAM4_0_0_0_PCI) Programmable Attribute Map 5 (PAM5_0_0_0_PCI) Programmable Attribute Map 6 (PAM6_0_0_0_PCI) Top of Memory (TOM_0_0_0_PCI) Top of Upper Usable DRAM (TOUUD_0_0_0_PCI) Base Data of Stolen Memory (BDSM_0_0_0_PCI) Base of GTT Stolen Memory (BGSM_0_0_0_PCI) TSEG Memory Base (TSEGMB_0_0_0_PCI) Top of Low Usable DRAM (TOLUD_0_0_0_PCI) Scratchpad Data (SKPD_0_0_0_PCI) Capabilities A (CAPID0_A_0_0_0_PCI) Capabilities B (CAPID0_B_0_0_0_PCI) Capabilities C (CAPID0_C_0_0_0_PCI) Capabilities E (CAPID0_E_0_0_0_PCI)
MCHBAR Base Address Register (MCHBAR_0_0_0_PCI)
Graphics Control (GGC_0_0_0_PCI)
Device Enable (DEVEN_0_0_0_PCI)
Protected Audio Video Path Control (PAVPC_0_0_0_PCI)
DMA Protected Range (DPR_0_0_0_PCI)
PCIEXBAR Base Address Register (PCIEXBAR_0_0_0_PCI)
SAFBAR PCI (SAFBAR_0_0_0_PCI)
CAPID_DEV_CDIE PCI (CAPID_DEV_CDIE_0_0_0_PCI)
Programmable Attribute Map 0 (PAM0_0_0_0_PCI)
Programmable Attribute Map 1 (PAM1_0_0_0_PCI)
Programmable Attribute Map 2 (PAM2_0_0_0_PCI)
Programmable Attribute Map 3 (PAM3_0_0_0_PCI)
Programmable Attribute Map 4 (PAM4_0_0_0_PCI)
Programmable Attribute Map 5 (PAM5_0_0_0_PCI)
Programmable Attribute Map 6 (PAM6_0_0_0_PCI)
Top of Memory (TOM_0_0_0_PCI)
Top of Upper Usable DRAM (TOUUD_0_0_0_PCI)
Base Data of Stolen Memory (BDSM_0_0_0_PCI)
Base of GTT Stolen Memory (BGSM_0_0_0_PCI)
TSEG Memory Base (TSEGMB_0_0_0_PCI)
Top of Low Usable DRAM (TOLUD_0_0_0_PCI)
Scratchpad Data (SKPD_0_0_0_PCI)
Capabilities A (CAPID0_A_0_0_0_PCI)
Capabilities B (CAPID0_B_0_0_0_PCI)
Capabilities C (CAPID0_C_0_0_0_PCI)
Capabilities E (CAPID0_E_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1) VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU)
VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2) CAPID0_F PCI (CAPID0_F_0_0_0_PCI)
CAPID0_F PCI (CAPID0_F_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1) Inter-Channel Decode Parameters (MAD_INTER_CHANNEL_0_0_0_MCHBAR) Intra-Channel 0 Decode Parameters (MAD_INTRA_CH0_0_0_0_MCHBAR) Intra-Channel 1 Decode Parameters (MAD_INTRA_CH1_0_0_0_MCHBAR) Channel 0 DIMM Characteristics (MAD_DIMM_CH0_0_0_0_MCHBAR) Channel 1 DIMM Characteristics (MAD_DIMM_CH1_0_0_0_MCHBAR) Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR) RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR) WrCAS Counter (PWM_WRCAS_COUNT_0_0_0_MCHBAR) PWM ACT COUNT 0 0 0 MCHBAR (PWM_ACT_COUNT_0_0_0_MCHBAR) PMON UNIT CONTROL 0 0 0 MCHBAR (PMON_UNIT_CONTROL_0_0_0_MCHBAR) PMON UNIT STATUS 0 0 0 MCHBAR (PMON_UNIT_STATUS_0_0_0_MCHBAR) PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_0) PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_1) PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_2) PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_3) PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_4) PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_0) PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_1) PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_2) PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_3) PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_4)
Inter-Channel Decode Parameters (MAD_INTER_CHANNEL_0_0_0_MCHBAR)
Intra-Channel 0 Decode Parameters (MAD_INTRA_CH0_0_0_0_MCHBAR)
Intra-Channel 1 Decode Parameters (MAD_INTRA_CH1_0_0_0_MCHBAR)
Channel 0 DIMM Characteristics (MAD_DIMM_CH0_0_0_0_MCHBAR)
Channel 1 DIMM Characteristics (MAD_DIMM_CH1_0_0_0_MCHBAR)
Memory Request Global Counter (PWM_TOTAL_REQCOUNT_0_0_0_MCHBAR)
RdCAS Counter (PWM_RDCAS_COUNT_0_0_0_MCHBAR)
WrCAS Counter (PWM_WRCAS_COUNT_0_0_0_MCHBAR)
PWM ACT COUNT 0 0 0 MCHBAR (PWM_ACT_COUNT_0_0_0_MCHBAR)
PMON UNIT CONTROL 0 0 0 MCHBAR (PMON_UNIT_CONTROL_0_0_0_MCHBAR)
PMON UNIT STATUS 0 0 0 MCHBAR (PMON_UNIT_STATUS_0_0_0_MCHBAR)
PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_0)
PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_1)
PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_2)
PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_3)
PMON COUNTER CONTROL 0 0 0 MCHBAR (PMON_COUNTER_CONTROL_0_0_0_MCHBAR_4)
PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_0)
PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_1)
PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_2)
PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_3)
PMON COUNTER DATA 0 0 0 MCHBAR (PMON_COUNTER_DATA_0_0_0_MCHBAR_4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2) PRE Command Timing (TC_PRE_0_0_0_MCHBAR) RD to RD Timings (TC_RDRD_0_0_0_MCHBAR) RD to WR Timings (TC_RDWR_0_0_0_MCHBAR) WR to RD Timings (TC_WRRD_0_0_0_MCHBAR) WR to WR Timings (TC_WRWR_0_0_0_MCHBAR) Roundtrip Latency (SC_Roundtrip_latency_0_0_0_MCHBAR) Power Down Timing (TC_PWRDN_0_0_0_MCHBAR) CAS Timing (TC_CAS_0_0_0_MCHBAR) WCK Timing (TC_WCK_0_0_0_MCHBAR) ACT Command Timing (TC_ACT_0_0_0_MCHBAR)
PRE Command Timing (TC_PRE_0_0_0_MCHBAR)
RD to RD Timings (TC_RDRD_0_0_0_MCHBAR)
RD to WR Timings (TC_RDWR_0_0_0_MCHBAR)
WR to RD Timings (TC_WRRD_0_0_0_MCHBAR)
WR to WR Timings (TC_WRWR_0_0_0_MCHBAR)
Roundtrip Latency (SC_Roundtrip_latency_0_0_0_MCHBAR)
Power Down Timing (TC_PWRDN_0_0_0_MCHBAR)
CAS Timing (TC_CAS_0_0_0_MCHBAR)
WCK Timing (TC_WCK_0_0_0_MCHBAR)
ACT Command Timing (TC_ACT_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3) TC REFm 0 0 0 MCHBAR (TC_REFm_0_0_0_MCHBAR) Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR) ZQCAL Control (TC_ZQCAL_0_0_0_MCHBAR) Refresh Timing Parameters (TC_RFTP_0_0_0_MCHBAR) Self-Refresh Exit Timing Parameters (TC_SREXITTP_0_0_0_MCHBAR)
TC REFm 0 0 0 MCHBAR (TC_REFm_0_0_0_MCHBAR)
Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR)
ZQCAL Control (TC_ZQCAL_0_0_0_MCHBAR)
Refresh Timing Parameters (TC_RFTP_0_0_0_MCHBAR)
Self-Refresh Exit Timing Parameters (TC_SREXITTP_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4) Memory On Package FUSES (MEMSS_PMA_CR_MOP_FUSES) MemSS PMA BIOS memory configuration register (MEMSS_PMA_CR_BIOS_MEM_CONFIG) MemSS PMA memory configuration register (MEMSS_PMA_CR_MEM_CONFIG) BIOS MRC Revision (MEMSS_PMA_CR_MRC_VERSION) Counter increments by 1 every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Lo) Counter increments by overflow value of PKG_MC_C0_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Hi) Counter increments by CMI PLL ratio every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Lo) Counter increments by overflow value of PKG_MC_C0_RATIO_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Hi)
Memory On Package FUSES (MEMSS_PMA_CR_MOP_FUSES)
MemSS PMA BIOS memory configuration register (MEMSS_PMA_CR_BIOS_MEM_CONFIG)
MemSS PMA memory configuration register (MEMSS_PMA_CR_MEM_CONFIG)
BIOS MRC Revision (MEMSS_PMA_CR_MRC_VERSION)
Counter increments by 1 every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Lo)
Counter increments by overflow value of PKG_MC_C0_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_Hi)
Counter increments by CMI PLL ratio every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Lo)
Counter increments by overflow value of PKG_MC_C0_RATIO_Lo for every SBCLK cycle when CMI PLL is locked (PKG_MC_C0_RATIO_Hi)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (BIOS_POST_CODE_0_0_0_MCHBAR_PCU) Cycle Sum of All Active Cores (PKG_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU) Cycle Sum of Any Active Core (PKG_IA_C0_ANY_0_0_0_MCHBAR_PCU) (PKG_IA_C0_ANY_RATIO_0_0_0_MCHBAR_PCU) (PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR_PCU) SA_PERF_STATUS0 (SA_PERF_STATUS0_0_0_0_MCHBAR_PCU) (PRIP_NRG_STTS_0_0_0_MCHBAR_PCU) (SECP_NRG_STTS_0_0_0_MCHBAR_PCU) Package power sku unit (PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR_PCU) Package energy status (PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR_PCU) sa perf status1 (SA_PERF_STATUS1_0_0_0_MCHBAR_PCU) Power Plane 0 Efficient Cycles (PP0_EFFICIENT_CYCLES_0_0_0_MCHBAR_PCU) (PP0_TEMPERATURE_0_0_0_MCHBAR_PCU) (RP_STATE_LIMITS_0_0_0_MCHBAR_PCU) GT PState CAP (GT_PSTATE_CAP_0_0_0_MCHBAR_PCU) Temperature Target (TEMPERATURE_TARGET_0_0_0_MCHBAR_PCU) (PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU) Thermal Status GT (THERM_STATUS_GT_0_0_0_MCHBAR_PCU) Thermal Interrupt GT (therm_interrupt_GT_0_0_0_MCHBAR_PCU) (DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU) DLVR RFI/EMI Control Register (RFI_EMI_CONTROL_0_0_0_MCHBAR_PCU) (CORE_PERF_MIN_MAX_0_0_0_MCHBAR) (PLATFORM_TEMPERATURE_CONTROL_1_0_0_0_MCHBAR) (PLATFORM_TEMPERATURE_CONTROL_2_0_0_0_MCHBAR) (PLATFORM_TEMPERATURE_CONTROL_3_0_0_0_MCHBAR) (BIOS_Mailbox_Data_0_0_0_MCHBAR_PCU) (BIOS_Mailbox_Interface_0_0_0_MCHBAR_PCU) (BIOS_RESET_CPL_0_0_0_MCHBAR_PCU) (DDR_THERM_CONTROL_0_0_0_MCHBAR_PCU) ISYS Control (ISYS_CONTROL_0_0_0_MCHBAR) (CONFIG_TDP_NOMINAL_0_0_0_MCHBAR_PCU) (CONFIG_TDP_LEVEL1_0_0_0_MCHBAR_PCU) (CONFIG_TDP_LEVEL2_0_0_0_MCHBAR_PCU) (CONFIG_TDP_CONTROL_0_0_0_MCHBAR_PCU) (TURBO_ACTIVATION_RATIO_0_0_0_MCHBAR_PCU) (OC_STATUS_0_0_0_MCHBAR_PCU) (BCLK_FREQ_0_0_0_MCHBAR)
(BIOS_POST_CODE_0_0_0_MCHBAR_PCU)
Cycle Sum of All Active Cores (PKG_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU)
Cycle Sum of Any Active Core (PKG_IA_C0_ANY_0_0_0_MCHBAR_PCU)
(PKG_IA_C0_ANY_RATIO_0_0_0_MCHBAR_PCU)
(PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR_PCU)
SA_PERF_STATUS0 (SA_PERF_STATUS0_0_0_0_MCHBAR_PCU)
(PRIP_NRG_STTS_0_0_0_MCHBAR_PCU)
(SECP_NRG_STTS_0_0_0_MCHBAR_PCU)
Package power sku unit (PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR_PCU)
Package energy status (PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR_PCU)
sa perf status1 (SA_PERF_STATUS1_0_0_0_MCHBAR_PCU)
Power Plane 0 Efficient Cycles (PP0_EFFICIENT_CYCLES_0_0_0_MCHBAR_PCU)
(PP0_TEMPERATURE_0_0_0_MCHBAR_PCU)
(RP_STATE_LIMITS_0_0_0_MCHBAR_PCU)
GT PState CAP (GT_PSTATE_CAP_0_0_0_MCHBAR_PCU)
Temperature Target (TEMPERATURE_TARGET_0_0_0_MCHBAR_PCU)
(PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU)
Thermal Status GT (THERM_STATUS_GT_0_0_0_MCHBAR_PCU)
Thermal Interrupt GT (therm_interrupt_GT_0_0_0_MCHBAR_PCU)
(DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU)
DLVR RFI/EMI Control Register (RFI_EMI_CONTROL_0_0_0_MCHBAR_PCU)
(CORE_PERF_MIN_MAX_0_0_0_MCHBAR)
(PLATFORM_TEMPERATURE_CONTROL_1_0_0_0_MCHBAR)
(PLATFORM_TEMPERATURE_CONTROL_2_0_0_0_MCHBAR)
(PLATFORM_TEMPERATURE_CONTROL_3_0_0_0_MCHBAR)
(BIOS_Mailbox_Data_0_0_0_MCHBAR_PCU)
(BIOS_Mailbox_Interface_0_0_0_MCHBAR_PCU)
(BIOS_RESET_CPL_0_0_0_MCHBAR_PCU)
(DDR_THERM_CONTROL_0_0_0_MCHBAR_PCU)
ISYS Control (ISYS_CONTROL_0_0_0_MCHBAR)
(CONFIG_TDP_NOMINAL_0_0_0_MCHBAR_PCU)
(CONFIG_TDP_LEVEL1_0_0_0_MCHBAR_PCU)
(CONFIG_TDP_LEVEL2_0_0_0_MCHBAR_PCU)
(CONFIG_TDP_CONTROL_0_0_0_MCHBAR_PCU)
(TURBO_ACTIVATION_RATIO_0_0_0_MCHBAR_PCU)
(OC_STATUS_0_0_0_MCHBAR_PCU)
(BCLK_FREQ_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - SAFBAR PMON Registers Part1
D0:F0 Host Bridge and DRAM Controller - SAFBAR PMON Registers Part1 reg hbo event counter cfg (pmon_overflow_status_register) unit control register (pmon_unit_control_register) reg hbo event counter ctrl (pmon_control_register_0) reg hbo event counter ctrl (pmon_control_register_1) reg hbo event counter ctrl (pmon_control_register_2) reg hbo event counter ctrl (pmon_control_register_3) reg hbo event counters (pmon_data_register_0) reg hbo event counters (pmon_data_register_1) reg hbo event counters (pmon_data_register_2) reg hbo event counters (pmon_data_register_3)
reg hbo event counter cfg (pmon_overflow_status_register)
unit control register (pmon_unit_control_register)
reg hbo event counter ctrl (pmon_control_register_0)
reg hbo event counter ctrl (pmon_control_register_1)
reg hbo event counter ctrl (pmon_control_register_2)
reg hbo event counter ctrl (pmon_control_register_3)
reg hbo event counters (pmon_data_register_0)
reg hbo event counters (pmon_data_register_1)
reg hbo event counters (pmon_data_register_2)
reg hbo event counters (pmon_data_register_3)
D0:F0 Host Bridge and DRAM Controller - SAFBAR PMON Registers Part2
D0:F0 Host Bridge and DRAM Controller - SAFBAR PMON Registers Part2 PMON Unit Control Register (NcuPmonUnitControl) PMON Unit Status Register (NcuPmonUnitStatus) PMON Data Register (NcuPmonCounter_0) PMON Counter Control Register (NcuPmonCounterControl_0) PMON Data Register (NcuPmonCounter_1) PMON Counter Control Register (NcuPmonCounterControl_1) PMON Global Control Register (NcuPmonGlobalControl) PMON Global Status Register (NcuPmonGlobalStatus)
PMON Unit Control Register (NcuPmonUnitControl)
PMON Unit Status Register (NcuPmonUnitStatus)
PMON Data Register (NcuPmonCounter_0)
PMON Counter Control Register (NcuPmonCounterControl_0)
PMON Data Register (NcuPmonCounter_1)
PMON Counter Control Register (NcuPmonCounterControl_1)
PMON Global Control Register (NcuPmonGlobalControl)
PMON Global Status Register (NcuPmonGlobalStatus)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Version Register (VER_REG_0_0_0_VTDBAR) Capability Register (CAP_REG_0_0_0_VTDBAR) Extended Capability Register (ECAP_REG_0_0_0_VTDBAR) Global Command Register (GCMD_REG_0_0_0_VTDBAR) General Status Register (GSTS_REG_0_0_0_VTDBAR) Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR) Context Command Register (CCMD_REG_0_0_0_VTDBAR) Fault Status Register (FSTS_REG_0_0_0_VTDBAR) Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR) Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR) Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR) Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR) Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR) Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR) Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR) Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR) Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR) Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR) Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR) Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR) Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR) Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR) Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR) Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR) Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR) Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR) IQ Error Info register (IQERCD_REG_0_0_0_VTDBAR) Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR) Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR) Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR) Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR) Page Request Status Register (PRS_REG_0_0_0_VTDBAR) Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR) Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR) Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR) Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR) MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR) MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR) Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR) Performance Monitoring Capabilities (PERFCAP_0_0_0_VTDBAR) Performance Monitoring Configuration Offset (PERFCFGOFF_0_0_0_VTDBAR) Performance Monitoring Freeze Offset (PERFFRZOFF_0_0_0_VTDBAR) Performance Monitoring Overflow Offset (PERFOVFOFF_0_0_0_VTDBAR) Performance Monitoring Counter Offset (PERFCNTOFF_0_0_0_VTDBAR) Performance Interrupt Status (PERFINTRSTS_0_0_0_VTDBAR) Performance Interrupt Control (PERFINTRCTL_0_0_0_VTDBAR) Performance Interrupt Data (PERFINTRDATA_0_0_0_VTDBAR) Performance Interrupt Address (PERFINTRADDR_0_0_0_VTDBAR) Performance Interrupt Upper Address (PERFINTRUADDR_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP0_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP1_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP2_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP3_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP4_0_0_0_VTDBAR) Enhanced Command (ECMD_0_0_0_VTDBAR) Enhanced Command Response (ERESP_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP3_0_0_0_VTDBAR) Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR) Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR) Invalidate Address Register (IVA_REG_0_0_0_VTDBAR) IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP0_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP1_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP2_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP3_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG4_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP4_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG5_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP5_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG6_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP6_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG7_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP7_0_0_0_VTDBAR) Performance Monitoring Counter Event Capabilities (PERFCNTRCAP7_EG0_0_0_0_VTDBAR) Performance Monitoring Freeze (PERFFRZ0_0_0_0_VTDBAR) Performance Monitoring Overflow Status (PERFOVFSTS0_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR0_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR1_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR2_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR3_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR4_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR5_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR6_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR7_0_0_0_VTDBAR)
Version Register (VER_REG_0_0_0_VTDBAR)
Capability Register (CAP_REG_0_0_0_VTDBAR)
Extended Capability Register (ECAP_REG_0_0_0_VTDBAR)
Global Command Register (GCMD_REG_0_0_0_VTDBAR)
General Status Register (GSTS_REG_0_0_0_VTDBAR)
Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR)
Context Command Register (CCMD_REG_0_0_0_VTDBAR)
Fault Status Register (FSTS_REG_0_0_0_VTDBAR)
Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR)
Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR)
Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR)
Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR)
Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR)
Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR)
Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR)
Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR)
Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR)
Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR)
Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR)
Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR)
Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR)
Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR)
Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR)
Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR)
Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR)
Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR)
IQ Error Info register (IQERCD_REG_0_0_0_VTDBAR)
Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR)
Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR)
Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR)
Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR)
Page Request Status Register (PRS_REG_0_0_0_VTDBAR)
Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR)
Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR)
Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR)
Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR)
MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR)
MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR)
Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR)
Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR)
Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR)
Performance Monitoring Capabilities (PERFCAP_0_0_0_VTDBAR)
Performance Monitoring Configuration Offset (PERFCFGOFF_0_0_0_VTDBAR)
Performance Monitoring Freeze Offset (PERFFRZOFF_0_0_0_VTDBAR)
Performance Monitoring Overflow Offset (PERFOVFOFF_0_0_0_VTDBAR)
Performance Monitoring Counter Offset (PERFCNTOFF_0_0_0_VTDBAR)
Performance Interrupt Status (PERFINTRSTS_0_0_0_VTDBAR)
Performance Interrupt Control (PERFINTRCTL_0_0_0_VTDBAR)
Performance Interrupt Data (PERFINTRDATA_0_0_0_VTDBAR)
Performance Interrupt Address (PERFINTRADDR_0_0_0_VTDBAR)
Performance Interrupt Upper Address (PERFINTRUADDR_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP0_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP1_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP2_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP3_0_0_0_VTDBAR)
Performance Monitoring Event Capabilities (PERFEVNTCAP4_0_0_0_VTDBAR)
Enhanced Command (ECMD_0_0_0_VTDBAR)
Enhanced Command Response (ERESP_0_0_0_VTDBAR)
Enhanced Command Capabilities (ECMD_CAP3_0_0_0_VTDBAR)
Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR)
Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR)
Invalidate Address Register (IVA_REG_0_0_0_VTDBAR)
IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR0_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP0_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR1_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP1_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR2_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP2_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR3_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP3_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG4_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR4_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP4_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG5_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR5_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP5_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG6_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR6_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP6_0_0_0_VTDBAR)
Performance Monitoring Counter Configuration (PERFCNTRCFG7_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR0_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR1_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR2_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR3_0_0_0_VTDBAR)
Performance Monitoring Filter Configuration (PERFCNTR7_FLTR4_0_0_0_VTDBAR)
Performance Monitoring Counter Capabilities (PERFCNTRCAP7_0_0_0_VTDBAR)
Performance Monitoring Counter Event Capabilities (PERFCNTRCAP7_EG0_0_0_0_VTDBAR)
Performance Monitoring Freeze (PERFFRZ0_0_0_0_VTDBAR)
Performance Monitoring Overflow Status (PERFOVFSTS0_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR0_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR1_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR2_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR3_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR4_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR5_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR6_0_0_0_VTDBAR)
Performance Monitoring Counter (PERFCNTR7_0_0_0_VTDBAR)
D10:F0 Platform Monitoring Technology (PMT) Registers
D10:F0 Platform Monitoring Technology (PMT) Registers Device ID and Vendor ID (VENDOR_ID_DEVICE_ID) Command and Status (COMMAND_STATUS) Revision ID and Class Code (REVISION_ID) Cache Line Size, Master Latency Timer, Header Type and BIST (CACHE_LINE_SIZE) Base Address (PM_BAR) Subsystem Vendor ID and Subsystem ID (SUBSYSTEM_VENDOR_ID) Capabilities Pointer (CAPABILITIES_POINTER) Interrupt line (INTERRUPT_LINE) PCIe Capability ID (PCIE_CAPID) Device Capabilities (DEV_CAP) PCIE Device Control and Status (DEV_CTL_STS) MSI CAPID, Message Control (MSI_CAPID_MC_0_10_0_PCI) Message Address (MA_0_10_0_PCI) Message Data (MD_0_10_0_PCI) Power Management Capabilities (PM_CAPID) Power Management Control Status (PM_CONTROL_STATUS) Interrupt Status (INTSTS_0_10_0_PCI) Telemetry Capability Header (TELEM_CAPABILITY_HEADER) Telemetry VSEC 0 (TELEM_VSEC_0) Telemetry VSEC 1 (TELEM_VSEC_1) Telemetry VSEC 2 (TELEM_VSEC_2) Watcher Capability Header (WATCHER_CAPABILITY_HEADER) Watcher VSEC 0 (WATCHER_VSEC_0) Watcher VSEC 1 (WATCHER_VSEC_1) Watcher VSEC 2 (WATCHER_VSEC_2) Crashlog VSEC 0 (CRASHLOG_VSEC_0) Crashlog VSEC 1 (CRASHLOG_VSEC_1) Crashlog VSEC 2 (CRASHLOG_VSEC_2)
Device ID and Vendor ID (VENDOR_ID_DEVICE_ID)
Command and Status (COMMAND_STATUS)
Revision ID and Class Code (REVISION_ID)
Cache Line Size, Master Latency Timer, Header Type and BIST (CACHE_LINE_SIZE)
Base Address (PM_BAR)
Subsystem Vendor ID and Subsystem ID (SUBSYSTEM_VENDOR_ID)
Capabilities Pointer (CAPABILITIES_POINTER)
Interrupt line (INTERRUPT_LINE)
PCIe Capability ID (PCIE_CAPID)
Device Capabilities (DEV_CAP)
PCIE Device Control and Status (DEV_CTL_STS)
MSI CAPID, Message Control (MSI_CAPID_MC_0_10_0_PCI)
Message Address (MA_0_10_0_PCI)
Message Data (MD_0_10_0_PCI)
Power Management Capabilities (PM_CAPID)
Power Management Control Status (PM_CONTROL_STATUS)
Interrupt Status (INTSTS_0_10_0_PCI)
Telemetry Capability Header (TELEM_CAPABILITY_HEADER)
Telemetry VSEC 0 (TELEM_VSEC_0)
Telemetry VSEC 1 (TELEM_VSEC_1)
Telemetry VSEC 2 (TELEM_VSEC_2)
Watcher Capability Header (WATCHER_CAPABILITY_HEADER)
Watcher VSEC 0 (WATCHER_VSEC_0)
Watcher VSEC 1 (WATCHER_VSEC_1)
Watcher VSEC 2 (WATCHER_VSEC_2)
Crashlog VSEC 0 (CRASHLOG_VSEC_0)
Crashlog VSEC 1 (CRASHLOG_VSEC_1)
Crashlog VSEC 2 (CRASHLOG_VSEC_2)
D11:F0 Vision Processing Unit
D11:F0 Vision Processing Unit Device ID and Vendor ID (DEVVENDID) Status and Command (STATUSCOMMAND) Revision ID and Class Code (REVCLASSCODE) Cache Line Latency Header and BIST (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Base Address Register (BAR2) Base Address Register High (BAR2_HIGH) Subsystem Vendor and Subsystem ID (SUBSYSTEMID) Expansion ROM Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt (INTERRUPTREG) PCIe Capabilities (PCIECAPREG) PCIe Device Capability (DEVCAPREG) PCIe Device Control Status (DEVCTRLSTAT) PCIe Device Capability2 (DEVCAPREG2) PCIe Device Control2 Status (DEVCTRLSTAT2) Power Management Capability ID (POWERCAPID) Power Management Control And Status (PMECTRLSTATUS) PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG) Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Input (GEN_INPUT_REG) MSI Capability (MSI_CAP_REG) MSI Message Low Address (MSI_ADDR_LOW) MSI Message High Address (MSI_ADDR_HIGH) MSI Message Data (MSI_MSG_DATA) MSI Mask (MSI_MASK) MSI Pending (MSI_PENDING) Manufacturers ID (MANID) ATS Extended Capability Header (ATS_EXT_CAP_HEAD) ATS Capability and Control (ATS_CAP_CONTROL_HEAD) PASID Capability Header (PASID_CAP_HEAD) PASID Capability and Control (PASID_CAP_CONTROL_REG) PRS Capability Header (PRS_CAP_HEAD) PRS Control and Status (PRS_CONTROL_STATUS_REG) PRS Page Request Capacity (PRS_PAGE_REQ_CAPACITY) PRS Page Request Allocation (PRS_PAGE_REQ_ALLOC) SIOV Capability Header 1 (SIOV_CAP_HEAD_1) SIOV Capability Header 2 (SIOV_CAP_HEAD_2) SIOV Capability Header 3 (SIOV_CAP_HEAD_3) SIOV Support Page Size (SIOV_SUPP_PAGE_SZ) SIOV System Page Size (SIOV_SYSTEM_PAGE_SZ) SIOV Internal Capabilities (SIOV_INTERNAL_CAPABILITIES)
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header and BIST (CLLATHEADERBIST)
Base Address Register (BAR)
Base Address Register High (BAR_HIGH)
Base Address Register1 (BAR1)
Base Address Register1 High (BAR1_HIGH)
Base Address Register (BAR2)
Base Address Register High (BAR2_HIGH)
Subsystem Vendor and Subsystem ID (SUBSYSTEMID)
Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt (INTERRUPTREG)
PCIe Capabilities (PCIECAPREG)
PCIe Device Capability (DEVCAPREG)
PCIe Device Control Status (DEVCTRLSTAT)
PCIe Device Capability2 (DEVCAPREG2)
PCIe Device Control2 Status (DEVCTRLSTAT2)
Power Management Capability ID (POWERCAPID)
Power Management Control And Status (PMECTRLSTATUS)
PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG)
Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Input (GEN_INPUT_REG)
MSI Capability (MSI_CAP_REG)
MSI Message Low Address (MSI_ADDR_LOW)
MSI Message High Address (MSI_ADDR_HIGH)
MSI Message Data (MSI_MSG_DATA)
MSI Mask (MSI_MASK)
MSI Pending (MSI_PENDING)
Manufacturers ID (MANID)
ATS Extended Capability Header (ATS_EXT_CAP_HEAD)
ATS Capability and Control (ATS_CAP_CONTROL_HEAD)
PASID Capability Header (PASID_CAP_HEAD)
PASID Capability and Control (PASID_CAP_CONTROL_REG)
PRS Capability Header (PRS_CAP_HEAD)
PRS Control and Status (PRS_CONTROL_STATUS_REG)
PRS Page Request Capacity (PRS_PAGE_REQ_CAPACITY)
PRS Page Request Allocation (PRS_PAGE_REQ_ALLOC)
SIOV Capability Header 1 (SIOV_CAP_HEAD_1)
SIOV Capability Header 2 (SIOV_CAP_HEAD_2)
SIOV Capability Header 3 (SIOV_CAP_HEAD_3)
SIOV Support Page Size (SIOV_SUPP_PAGE_SZ)
SIOV System Page Size (SIOV_SYSTEM_PAGE_SZ)
SIOV Internal Capabilities (SIOV_INTERNAL_CAPABILITIES)
D2:F0 Processor Graphics
D2:F0 Processor Graphics Vendor Identification (VID2_0_2_0_PCI) Device Identification (DID2_0_2_0_PCI) PCI Command (PCICMD_0_2_0_PCI) PCI Status (PCISTS2_0_2_0_PCI) Revision Identification and Class Code register (RID2_CC_0_2_0_PCI) Cache Line Size (CLS_0_2_0_PCI) Master Latency Timer (MLT2_0_2_0_PCI) Header Type (HDR2_0_2_0_PCI) Built In Self Test (BIST_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI) Local Memory Bar (LMEMBAR0_0_2_0_PCI) Local Memory Bar (LMEMBAR1_0_2_0_PCI) Subsystem Vendor Identification (SVID2_0_2_0_PCI) Subsystem Identification (SID2_0_2_0_PCI) Video BIOS ROM Base Address (ROMADR_0_2_0_PCI) Capabilities Pointer (CAPPOINT_0_2_0_PCI) Interrupt Line (INTRLINE_0_2_0_PCI) Interrupt Pin (INTRPIN_0_2_0_PCI) Minimum Grant (MINGNT_0_2_0_PCI) Maximum Latency (MAXLAT_0_2_0_PCI) Capability Identifier (CAPID0_0_2_0_PCI) Capabilities Control (CAPCTRL0_0_2_0_PCI) Capabilities A (CAPID0_A_0_2_0_PCI) PCI Mirror of GMCH Graphics Control (MGGC0_0_2_0_PCI) PCI Express Capability Header (PCIECAPHDR_0_2_0_PCI) PCI Express Capability (PCIECAP_0_2_0_PCI) Device Capabilities (DEVICECAP_0_2_0_PCI) PCI Express Device Control (DEVICECTL_0_2_0_PCI) PCI Express Device Status Register (DEVICESTS_0_2_0_PCI) Link Capabilities (LINKCAP_0_2_0_PCI) Link Control and Status (LINKCTRLSTS_0_2_0_PCI) Device Capabilities 2 (DEVCAP2_0_2_0_PCI) Link Capabilities 2 (LINKCAP2_0_2_0_PCI) Message Signaled Interrupts Capability ID (MSI_CAPID_0_2_0_PCI) Message Control (MC_0_2_0_PCI) Message Address (MA0_0_2_0_PCI) Message Address (MA1_0_2_0_PCI) Message Data (MD_0_2_0_PCI) MSI Mask Bits (MSI_MASK_0_2_0_PCI) MSI Pending Bits (MSI_PEND_0_2_0_PCI) Power Management Capabilities ID (PMCAPID_0_2_0_PCI) Power Management Capabilities (PMCAP_0_2_0_PCI) Power Management Control and Status (PMCS_0_2_0_PCI) Graphics System Event (GSE_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC1_0_2_0_PCI) Stepping Revision ID (SRID_0_2_0_PCI) ASL Storage (ASLS_0_2_0_PCI) ARI Extended Capability Header (ARI_CAPHDR_0_2_0_PCI) ARI Capability (ARI_CAP_0_2_0_PCI) ARI Control (ARI_CTRL_0_2_0_PCI) PASID Extended Capability Header (PASID_EXTCAP_0_2_0_PCI) PASID Capability (PASID_CAP_0_2_0_PCI) PASID Control (PASID_CTRL_0_2_0_PCI) ATS Extended Capability Header (ATS_EXTCAP_0_2_0_PCI) ATS Capability (ATS_CAP_0_2_0_PCI) ATS Control (ATS_CTRL_0_2_0_PCI) VF Resizable Capability Header (VF_RESIZE_CAPHDR_0_2_0_PCI) VF Resizable Capability (VF_RESIZE_CAP_0_2_0_PCI) VF Resizable Control (VF_RESIZABLE_CTRL_0_2_0_PCI) SRIOV Extended Capability Header (SRIOV_ECAPHDR_0_2_0_PCI) SRIOV Capabilities (SRIOV_CAP_0_2_0_PCI) SRIOV Control Register (SRIOV_CTRL_0_2_0_PCI) SRIOV Status (SRIOV_STS_0_2_0_PCI) SRIOV Initial VFs (SRIOV_INITVFS_0_2_0_PCI) SRIOV Total VFs (SRIOV_TOTVFS_0_2_0_PCI) Number Of VFs (SRIOV_NUMOFVFS_0_2_0_PCI) First VF Offset (FIRST_VF_OFFSET_0_2_0_PCI) VF Stride (VF_STRIDE_0_2_0_PCI) VF Device ID (VF_DEVICEID_0_2_0_PCI) Supported Page Sizes (SUPPORTED_PAGE_SIZES_0_2_0_PCI) System Page Sizes (SYSTEM_PAGE_SIZES_0_2_0_PCI) VF BAR0 Lower DWORD (VF_BAR0_LDW_0_2_0_PCI) VF BAR0 Upper DWORD (VF_BAR0_UDW_0_2_0_PCI) LTR Extended Capability Header (LTR_CAPHDR_0_2_0_PCI) Max Snoop Latency Register (MAX_SNP_LAT_0_2_0_PCI) Max No Snoop Latency Register (MAX_NOSNP_LAT_0_2_0_PCI) PF Resizable Capability Header (PF_RESIZE_CAPHDR_0_2_0_PCI) PF Resizable BAR Capability (PF_RESIZE_BAR_CAP_0_2_0_PCI) PF Resizable BAR Control (PF_RESIZABLE_BAR_CTRL_0_2_0_PCI)
Vendor Identification (VID2_0_2_0_PCI)
Device Identification (DID2_0_2_0_PCI)
PCI Command (PCICMD_0_2_0_PCI)
PCI Status (PCISTS2_0_2_0_PCI)
Revision Identification and Class Code register (RID2_CC_0_2_0_PCI)
Cache Line Size (CLS_0_2_0_PCI)
Master Latency Timer (MLT2_0_2_0_PCI)
Header Type (HDR2_0_2_0_PCI)
Built In Self Test (BIST_0_2_0_PCI)
Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI)
Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI)
Local Memory Bar (LMEMBAR0_0_2_0_PCI)
Local Memory Bar (LMEMBAR1_0_2_0_PCI)
Subsystem Vendor Identification (SVID2_0_2_0_PCI)
Subsystem Identification (SID2_0_2_0_PCI)
Video BIOS ROM Base Address (ROMADR_0_2_0_PCI)
Capabilities Pointer (CAPPOINT_0_2_0_PCI)
Interrupt Line (INTRLINE_0_2_0_PCI)
Interrupt Pin (INTRPIN_0_2_0_PCI)
Minimum Grant (MINGNT_0_2_0_PCI)
Maximum Latency (MAXLAT_0_2_0_PCI)
Capability Identifier (CAPID0_0_2_0_PCI)
Capabilities Control (CAPCTRL0_0_2_0_PCI)
Capabilities A (CAPID0_A_0_2_0_PCI)
PCI Mirror of GMCH Graphics Control (MGGC0_0_2_0_PCI)
PCI Express Capability Header (PCIECAPHDR_0_2_0_PCI)
PCI Express Capability (PCIECAP_0_2_0_PCI)
Device Capabilities (DEVICECAP_0_2_0_PCI)
PCI Express Device Control (DEVICECTL_0_2_0_PCI)
PCI Express Device Status Register (DEVICESTS_0_2_0_PCI)
Link Capabilities (LINKCAP_0_2_0_PCI)
Link Control and Status (LINKCTRLSTS_0_2_0_PCI)
Device Capabilities 2 (DEVCAP2_0_2_0_PCI)
Link Capabilities 2 (LINKCAP2_0_2_0_PCI)
Message Signaled Interrupts Capability ID (MSI_CAPID_0_2_0_PCI)
Message Control (MC_0_2_0_PCI)
Message Address (MA0_0_2_0_PCI)
Message Address (MA1_0_2_0_PCI)
Message Data (MD_0_2_0_PCI)
MSI Mask Bits (MSI_MASK_0_2_0_PCI)
MSI Pending Bits (MSI_PEND_0_2_0_PCI)
Power Management Capabilities ID (PMCAPID_0_2_0_PCI)
Power Management Capabilities (PMCAP_0_2_0_PCI)
Power Management Control and Status (PMCS_0_2_0_PCI)
Graphics System Event (GSE_0_2_0_PCI)
Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI)
Device 2 Mirror of Protected Audio Video Path Control (PAVPC1_0_2_0_PCI)
Stepping Revision ID (SRID_0_2_0_PCI)
ASL Storage (ASLS_0_2_0_PCI)
ARI Extended Capability Header (ARI_CAPHDR_0_2_0_PCI)
ARI Capability (ARI_CAP_0_2_0_PCI)
ARI Control (ARI_CTRL_0_2_0_PCI)
PASID Extended Capability Header (PASID_EXTCAP_0_2_0_PCI)
PASID Capability (PASID_CAP_0_2_0_PCI)
PASID Control (PASID_CTRL_0_2_0_PCI)
ATS Extended Capability Header (ATS_EXTCAP_0_2_0_PCI)
ATS Capability (ATS_CAP_0_2_0_PCI)
ATS Control (ATS_CTRL_0_2_0_PCI)
VF Resizable Capability Header (VF_RESIZE_CAPHDR_0_2_0_PCI)
VF Resizable Capability (VF_RESIZE_CAP_0_2_0_PCI)
VF Resizable Control (VF_RESIZABLE_CTRL_0_2_0_PCI)
SRIOV Extended Capability Header (SRIOV_ECAPHDR_0_2_0_PCI)
SRIOV Capabilities (SRIOV_CAP_0_2_0_PCI)
SRIOV Control Register (SRIOV_CTRL_0_2_0_PCI)
SRIOV Status (SRIOV_STS_0_2_0_PCI)
SRIOV Initial VFs (SRIOV_INITVFS_0_2_0_PCI)
SRIOV Total VFs (SRIOV_TOTVFS_0_2_0_PCI)
Number Of VFs (SRIOV_NUMOFVFS_0_2_0_PCI)
First VF Offset (FIRST_VF_OFFSET_0_2_0_PCI)
VF Stride (VF_STRIDE_0_2_0_PCI)
VF Device ID (VF_DEVICEID_0_2_0_PCI)
Supported Page Sizes (SUPPORTED_PAGE_SIZES_0_2_0_PCI)
System Page Sizes (SYSTEM_PAGE_SIZES_0_2_0_PCI)
VF BAR0 Lower DWORD (VF_BAR0_LDW_0_2_0_PCI)
VF BAR0 Upper DWORD (VF_BAR0_UDW_0_2_0_PCI)
LTR Extended Capability Header (LTR_CAPHDR_0_2_0_PCI)
Max Snoop Latency Register (MAX_SNP_LAT_0_2_0_PCI)
Max No Snoop Latency Register (MAX_NOSNP_LAT_0_2_0_PCI)
PF Resizable Capability Header (PF_RESIZE_CAPHDR_0_2_0_PCI)
PF Resizable BAR Capability (PF_RESIZE_BAR_CAP_0_2_0_PCI)
PF Resizable BAR Control (PF_RESIZABLE_BAR_CTRL_0_2_0_PCI)
D4:F0 Dynamic Tuning Technology
D4:F0 Dynamic Tuning Technology Vendor ID (VID_0_4_0_PCI) Device ID (DID_0_4_0_PCI) PCI Command (PCICMD_0_4_0_PCI) PCI Status (PCISTS_0_4_0_PCI) Revision ID (RID_0_4_0_PCI) Class Code (CC_0_4_0_PCI) Extended Class Code (CC_0_4_0_NOPI_PCI) Cache Line Size (CLS_0_4_0_PCI) Master Latency Timer (MLT_0_4_0_PCI) Header Type (HDR_0_4_0_PCI) Built In Self Test (BIST_0_4_0_PCI) Thermal Controller Base Address (TMBAR_0_4_0_PCI) Subsystem Vendor ID (SVID_0_4_0_PCI) Subsystem ID (SID_0_4_0_PCI) Capabilities Pointer (CAPPOINT_0_4_0_PCI) Interrupt Line Register (INTRLINE_0_4_0_PCI) Interrupt Pin Register (INTRPIN_0_4_0_PCI) Minimum Guaranteed (MINGNT_0_4_0_PCI) Maximum Latency (MAXLAT_0_4_0_PCI) PM Capabilities (PM_CAPID_0_4_0_PCI)
Vendor ID (VID_0_4_0_PCI)
Device ID (DID_0_4_0_PCI)
PCI Command (PCICMD_0_4_0_PCI)
PCI Status (PCISTS_0_4_0_PCI)
Revision ID (RID_0_4_0_PCI)
Class Code (CC_0_4_0_PCI)
Extended Class Code (CC_0_4_0_NOPI_PCI)
Cache Line Size (CLS_0_4_0_PCI)
Master Latency Timer (MLT_0_4_0_PCI)
Header Type (HDR_0_4_0_PCI)
Built In Self Test (BIST_0_4_0_PCI)
Thermal Controller Base Address (TMBAR_0_4_0_PCI)
Subsystem Vendor ID (SVID_0_4_0_PCI)
Subsystem ID (SID_0_4_0_PCI)
Capabilities Pointer (CAPPOINT_0_4_0_PCI)
Interrupt Line Register (INTRLINE_0_4_0_PCI)
Interrupt Pin Register (INTRPIN_0_4_0_PCI)
Minimum Guaranteed (MINGNT_0_4_0_PCI)
Maximum Latency (MAXLAT_0_4_0_PCI)
PM Capabilities (PM_CAPID_0_4_0_PCI)
D5:F0 Image Processing Unit
D5:F0 Image Processing Unit Device ID and Vendor ID (DEVVENDID) Status and Command (STATUSCOMMAND) Revision ID and Class Code (REVCLASSCODE) Cache Line Latency Header Bist (CLLATHEADERBIST) Base Address (BAR) Base Address High (BAR_HIGH) Base Address1 (BAR1) Base Address1 High (BAR1_HIGH) Base Address (BAR2) Base Address High (BAR2_HIGH) Subsystem Vendor And Subsystem ID (SUBSYSTEMID) Expansion ROM Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt (INTERRUPTREG) PCIe Capabilities (PCIECAPREG) PCIe Device Capability (DEVCAPREG) PCIe Device Control Status (DEVCTRLSTAT) PCIe Device Capability2 (DEVCAPREG2) PCIe Device Control2 Status (DEVCTRLSTAT2) Power Management Capability ID (POWERCAPID) Power Management Control and Status (PMECTRLSTATUS) PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG) Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Input (GEN_INPUT_REG) MSI Capability (MSI_CAP_REG) MSI Message Low Address (MSI_ADDR_LOW) MSI Message High Address (MSI_ADDR_HIGH) MSI Message Data (MSI_MSG_DATA) MSI Mask (MSI_MASK) MSI Pending (MSI_PENDING) Manufacturers ID (MANID) ATS Extended Capability Header (ATS_EXT_CAP_HEAD) ATS Capability and Control (ATS_CAP_CONTROL_HEAD)
Device ID and Vendor ID (DEVVENDID)
Status and Command (STATUSCOMMAND)
Revision ID and Class Code (REVCLASSCODE)
Cache Line Latency Header Bist (CLLATHEADERBIST)
Base Address (BAR)
Base Address High (BAR_HIGH)
Base Address1 (BAR1)
Base Address1 High (BAR1_HIGH)
Base Address (BAR2)
Base Address High (BAR2_HIGH)
Subsystem Vendor And Subsystem ID (SUBSYSTEMID)
Expansion ROM Base Address (EXPANSION_ROM_BASEADDR)
Capabilities Pointer (CAPABILITYPTR)
Interrupt (INTERRUPTREG)
PCIe Capabilities (PCIECAPREG)
PCIe Device Capability (DEVCAPREG)
PCIe Device Control Status (DEVCTRLSTAT)
PCIe Device Capability2 (DEVCAPREG2)
PCIe Device Control2 Status (DEVCTRLSTAT2)
Power Management Capability ID (POWERCAPID)
Power Management Control and Status (PMECTRLSTATUS)
PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD)
Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG)
Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG)
Device Idle Pointer (DEVICE_IDLE_POINTER_REG)
D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG)
General Purpose Input (GEN_INPUT_REG)
MSI Capability (MSI_CAP_REG)
MSI Message Low Address (MSI_ADDR_LOW)
MSI Message High Address (MSI_ADDR_HIGH)
MSI Message Data (MSI_MSG_DATA)
MSI Mask (MSI_MASK)
MSI Pending (MSI_PENDING)
Manufacturers ID (MANID)
ATS Extended Capability Header (ATS_EXT_CAP_HEAD)
ATS Capability and Control (ATS_CAP_CONTROL_HEAD)

PCI Status (PCISTS_0_4_0_PCI) – Offset 6

PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant Master Abort (MA) and PCI compliant Target Abort (TA).
PCISTS also indicates the DEVSEL# timing that has been set by the DTT Device.

Bit Range

Default

Access

Field Name and Description

15

0h

RO

Detected Parity Error (DPE)

The DTT device does not implement this bit and it is hardwired to a 0.

14

0h

RO

Signaled System Error (SSE)

This bit is hardwired to zero.
The DTT Device never asserts SERR#, and therefore it has no need to implement this bit.

13

0h

RO

Received Master Abort Status (RURS)

The DTT device does not implement this bit and it is hardwired to a 0.

12

0h

RO

Received Target Abort Status (RCAS)

The DTT device does not implement this bit and it is hardwired to a 0.

11

0h

RO

Signaled Target Abort Status (STAS)

This bit is hardwired to 0.
The DTT Device will not generate a Target Abort DMI completion packet or Special Cycle, and therefore it has no need to implement this bit.

10:9

0h

RO

DEVSEL# Timing Status (DEVT)

These bits are hardwired to 0.
Device 4 does not physically connect to PCI_​A.

8

0h

RO

Master Data Parity Error Detected (DPD)

This bit is hardwired to 0.
PERR signaling and messaging are not implemented by the DTT Device, and therefore it has no need to implement this bit.

7

1h

RO

(FB2BC)

Fast Back-to-Back Capable. IOP legacy - set to '1 though no fast b2b will be enabled.

6

0h

RO

Reserved

5

0h

RO

Primary 66 MHz Capable (PCI66M)

The DTT device does not implement this bit and it is hardwired to a 0.

4

1h

RO

Capabilities List (CLIST)

Capabilities list. DTT supports the extended capabilities linked-list structure.
CAPPOINT_​0_​4_​0_​PCI provides the offset for the first linked-list element, the MSI capabilities.

3

0h

RW/V

Interrupt Status (IS)

Interrupt Status. Set by HW to '1 when an interrupt is pending and reset by HW to '0 once the interrupt is cleared by SW.

2:0

0h

RO

Reserved

Revision ID (RID_0_4_0_PCI)