15:11

0h

RO

Reserved

10

1h

RW

Interrupt Disable (INTDIS)

Interrupt (INTA) Disable. Camarillo no longer supports INTA generation.

9

0h

RO

(FB2BE)

Fast Back-to-Back Enable. No Camarillo support.

8

0h

RO

SERR Reporting Enable (SERRE)

The DTT device does not implement this bit and it is hardwired to a 0.

7

0h

RO

Address/Data Stepping (ADSTEP)

The DTT device does not implement this bit and it is hardwired to a 0.

6

0h

RO

Parity Error Response Enable (PERRE)

This bit is hardwired to 0. The DTT Device belongs to the category of devices that does not corrupt programs or data in system memory or hard drives. It therefore ignores any parity error that it detects and continues with normal operation.

5

0h

RO

Video Palette Snooping (VGASNOOP)

The DTT device does not implement this bit and it is hardwired to a 0.

4

0h

RO

(MWIE)

This bit is hardwired to 0.
The DTT Device will never issue memory write and invalidate commands, and therefore has no need to implement this bit.

3

0h

RO

Special Cycle Enable (SCE)

Reserved per PCI-Express and PCI bridge spec.

2

0h

RW

Bus Master Enable (BME)

The DTT Device is enabled to function as a PCI-compliant bus master when this bit is set.
If it is not set, bus mastering is disabled.

1

0h

RW

Memory Access Enable (MAE)

The DTT Device will allow access to thermal registers when this bit is set. If it is not set, access to memory mapped thermal registers is disabled.

0

0h

RO

I/O Access Enable (IOAE)

The DTT device does not implement this bit and it is hardwired to a 0.