Intel® Core™ Ultra 200V Series Processors

Datasheet, Volume 1 of 2

ID Date Version Classification
829568 05/27/2025 004 Confidential
Document Table of Contents
Document Table of Contents
Legal Disclaimer Revision History Introduction Processor and Device IDs Package Mechanical Specifications Memory Mapping Security Technologies Intel® Virtualization Technology (Intel® VT) Instructions Set Enhancements Intel® Image Processing Unit (Intel® IPU7) Intel® Neural Processing Unit (Intel® NPU) Audio Voice and Speech Power Management Power Delivery Electrical Specifications Thermal Management System Clocks Real Time Clock (RTC) Integrated System Memory USB Type-C* Sub System Universal Serial Bus (USB) PCI Express* (PCIe*) Graphics Display Processor Sideband Signals General Purpose Input and Output Interrupt Timer Subsystem (ITSS) Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers Gigabit Ethernet Controller Connectivity Integrated (CNVi) Controller Link Integrated Sensor Hub (ISH) System Management Interface and SMLink Serial Peripheral Interface (SPI) Enhanced Serial Peripheral Interface (eSPI) Intel® Serial IO Generic SPI (GSPI) Controllers Touch Host Controller (THC) Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Private Configuration Space Port ID Testability and Monitoring Miscellaneous Signals
Legal Disclaimer
Revision History
Introduction
Introduction Processor Volatility Statement Package Dimensions Supported Technologies Power Management Support Thermal Management Support Ballout Information Processor Testability Operating Systems Support Terminology and Special Marks Flexible High Speed I/O Related Documents
Processor Volatility Statement
Package Dimensions
Supported Technologies
Supported Technologies API Support (Windows*) Firmware Resiliency
API Support (Windows*)
Firmware Resiliency
Power Management Support
Power Management Support Processor Core Power Management System Power Management Memory Controller Power Management Processor Graphics Power Management
Processor Core Power Management
System Power Management
Memory Controller Power Management
Processor Graphics Power Management
Thermal Management Support
Ballout Information
Processor Testability
Operating Systems Support
Terminology and Special Marks
Flexible High Speed I/O
Flexible High Speed I/O Intel® Core™ Ultra 200V Series Processor Flexible I/O Lane Selection
Intel® Core™ Ultra 200V Series Processor
Flexible I/O Lane Selection
Related Documents
Processor and Device IDs
Processor and Device IDs CPUID PCI Configuration Header Device IDs Revision IDs
CPUID
PCI Configuration Header
Device IDs
Revision IDs
Package Mechanical Specifications
Package Mechanical Specifications Package Mechanical Attributes Package Loading and Tile Pressure Specifications Package Storage Specifications
Package Mechanical Attributes
Package Loading and Tile Pressure Specifications
Package Loading and Tile Pressure Specifications Static Compressive Load Specification Maximum Pressure Specifications
Static Compressive Load Specification
Maximum Pressure Specifications
Package Storage Specifications
Memory Mapping
Memory Mapping Functional Description Memory Map
Functional Description
PCI Devices and Functions Fixed I/O Address Ranges Variable I/O Decode Ranges
PCI Devices and Functions
Fixed I/O Address Ranges
Variable I/O Decode Ranges
Memory Map
Memory Map Boot Block Update Scheme
Boot Block Update Scheme
Security Technologies
Security Technologies Intel® Converged Boot Guard and Intel® TXT Crypto Acceleration Instructions Intel® Secure Key Execute Disable Bit Intel® Supervisor Mode Execution Protection (Intel® SMEP) Intel® Supervisor Mode Access Protection (Intel® SMAP) User Mode Instruction Prevention (UMIP) Intel® System Resources Defense and Intel® System Security Report Intel® Total Memory Encryption - Multi-Key Control-flow Enforcement Technology (Intel® CET) BIOS Guard Intel® Platform Trust Technology Linear Address Space Separation (LASS) Security Firmware Engines
Intel® Converged Boot Guard and Intel® TXT
Crypto Acceleration Instructions
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ) Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions) New Cryptographic Acceleration Instructions
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)
Perform Carry-Less Multiplication Quad Word Instruction (PCLMULQDQ)
Intel® Secure Hash Algorithm Extensions (Intel® SHA Extensions)
New Cryptographic Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Protection (Intel® SMEP)
Intel® Supervisor Mode Access Protection (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Intel® System Resources Defense and Intel® System Security Report
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
Control-flow Enforcement Technology (Intel® CET) Shadow Stack Indirect Branch Tracking
Shadow Stack
Indirect Branch Tracking
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Security Firmware Engines
Intel® Converged Security and Management Engine (Intel® CSME) Intel® Silicon Security Engine Intel® Graphics Security Controller (Intel® GSC) Intel® Partner Security Engine
Intel® Converged Security and Management Engine (Intel® CSME)
Intel® Silicon Security Engine
Intel® Graphics Security Controller (Intel® GSC)
Intel® Partner Security Engine
Intel® Virtualization Technology (Intel® VT)
Intel® Virtualization Technology (Intel® VT) Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x) Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Intel® APIC Virtualization Technology (Intel® APICv)
Intel® Virtualization Technology (Intel® VT) for Intel® 64 and Intel® Architecture (Intel® VT-x)
Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)
Intel® APIC Virtualization Technology (Intel® APICv)
Instructions Set Enhancements
Instructions Set Enhancements CMPccXADD Linear Address Masking (LAM) SW Resource Prioritization
CMPccXADD
Linear Address Masking (LAM)
SW Resource Prioritization
Intel® Image Processing Unit (Intel® IPU7)
Platform Imaging Infrastructure Intel® Image Processing Unit (Intel® IPU7) Camera / Integrated ISP
Platform Imaging Infrastructure
Intel® Image Processing Unit (Intel® IPU7)
Camera / Integrated ISP
Camera Pipe Support MIPI* CSI-2 Camera Interconnect
Camera Pipe Support
MIPI* CSI-2 Camera Interconnect
MIPI* CSI-2 Camera Interconnect Camera Control Logic Camera Modules CSI2 Signal Description CSI2 Configuration Options
Camera Control Logic
Camera Modules
CSI2
Signal Description
CSI2 Configuration Options
Intel® Neural Processing Unit (Intel® NPU)
Intel® Neural Processing Unit (Intel® NPU) Functional Description
Functional Description
Functional Description HOST Control Deep Learning Accelerators (NCE)
HOST Control
Deep Learning Accelerators (NCE)
Deep Learning Accelerators (NCE) Feature Set NCE Tile ACTIVATION-SHAVE (ACT-SHAVE) Data Processing Unit (DPU)
Feature Set
NCE Tile
ACTIVATION-SHAVE (ACT-SHAVE)
Data Processing Unit (DPU)
Audio Voice and Speech
Audio Voice and Speech Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities Audio DSP Capabilities Intel® High Definition Audio Interface Capabilities Direct Attached Digital Microphone (PDM) Interface USB Audio Offload Support Intel® Display Audio Interface MIPI® SoundWire* Interface Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Power Management
Power Management System Power States, Advanced Configuration and Power Interface (ACPI) Legacy Power Management Support Functional Description Processor Power and Efficient P/LP E Cores Power Management Processor Graphics Power Management TCSS Power State Power and Performance Technologies Deprecated Technology Power and Internal Signals
System Power States, Advanced Configuration and Power Interface (ACPI)
Legacy Power Management Support
ALT Access Mode Legacy Power Management Theory of Operation
ALT Access Mode
Legacy Power Management Theory of Operation
Functional Description
Features Power Saving Features SMI#/SCI Generation Sleep States Event Input Signals and Their Usage System Power Supplies, Planes, and Signals Reset Behavior
Features
Power Saving Features
SMI#/SCI Generation
Sleep States
Event Input Signals and Their Usage
System Power Supplies, Planes, and Signals
Reset Behavior
Processor Power and Efficient P/LP E Cores Power Management
Processor Power and Efficient P/LP E Cores Power Management OS/HW Controlled P-states Low-Power Idle States Requesting the Low-Power Idle States Processor P/LP E Core C-State Rules Package C-States Package C-States and Display Resolutions
OS/HW Controlled P-states
Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Low-Power Idle States
Requesting the Low-Power Idle States
Processor P/LP E Core C-State Rules
Package C-States
Package C-States and Display Resolutions
Processor Graphics Power Management
Processor Graphics Power Management Memory Power Savings Technologies Display Power Savings Technologies Processor Graphics Core Power Savings Technologies
Memory Power Savings Technologies
Display Power Savings Technologies
Processor Graphics Core Power Savings Technologies
TCSS Power State
Power and Performance Technologies
Power and Performance Technologies Intel® Thread Director Intel® Smart Cache Technology P-core and LP E-core Level 0, Level 1 and Level 2 Caches Ring Interconnect Intel® Hybrid Technology Intel® Turbo Boost Max Technology 3.0 Intel® Turbo Boost Technology 2.0 Intel® Adaptive Boost Technology Intel System Agent Enhanced SpeedStep® Technology Enhanced Intel SpeedStep® Technology Intel® Speed Shift Technology Intel® 64 Architecture x2APIC Intel® Advanced Vector Extensions 2 (Intel® AVX2) Intel® Dynamic Tuning Technology (Intel® DTT) User Mode Wait Instructions Cache Line Write Back (CLWB)
Intel® Thread Director
Intel® Smart Cache Technology
P-core and LP E-core Level 0, Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Max Technology 3.0
Intel® Turbo Boost Technology 2.0
Intel® Turbo Boost Technology 2.0 Intel® Turbo Boost Technology 2.0 Power Monitoring Intel® Turbo Boost Technology 2.0 Power Control Intel® Turbo Boost Technology 2.0 Frequency
Intel® Turbo Boost Technology 2.0 Power Monitoring
Intel® Turbo Boost Technology 2.0 Power Control
Intel® Turbo Boost Technology 2.0 Frequency
Intel® Adaptive Boost Technology
Intel System Agent Enhanced SpeedStep® Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel® 64 Architecture x2APIC
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Advanced Vector Extensions 2 (Intel® AVX2) AI Acceleration Extensions in Intel® AVX2
AI Acceleration Extensions in Intel® AVX2
Intel® Dynamic Tuning Technology (Intel® DTT)
User Mode Wait Instructions
Cache Line Write Back (CLWB)
Deprecated Technology
Power and Internal Signals
Signal Description Power Sequencing Signals Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Power Sequencing Signals
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Power Delivery
Power and Ground Signals Digital Linear Voltage Regulator (DLVR) Fast V-Mode (FVM) Current Excursion Protection (CEP) Thermally Equal Turbo-boost Algorithm (ThETA)
Power and Ground Signals
Digital Linear Voltage Regulator (DLVR)
Fast V-Mode (FVM)
Current Excursion Protection (CEP)
Thermally Equal Turbo-boost Algorithm (ThETA)
Electrical Specifications
Thermal Management
Thermal Management Package Thermal Management Processor Base Power Thermal and Power Specifications Processor Line Thermal and Power Specifications Error and Thermal Protection Signals Thermal Sensor
Package Thermal Management
Package Thermal Management Thermal Considerations Thermal Management Features Assured Power (cTDP) Intel® Memory Thermal Management
Thermal Considerations
Thermal Considerations Package Power Control Platform Power Control Turbo Time Parameter (Tau)
Package Power Control
Platform Power Control
Turbo Time Parameter (Tau)
Thermal Management Features
Thermal Management Features Skin Temperature Control (STC) Adaptive Thermal Monitor Digital Thermal Sensor PROCHOT# Signal PROCHOT Demotion Algorithm Voltage Regulator Protection using PROCHOT# Thermal Solution Design and PROCHOT# Behavior Low-Power States and PROCHOT# Behavior THERMTRIP# Signal Critical Temperature Detection
Skin Temperature Control (STC)
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THERMTRIP# Signal
Critical Temperature Detection
Assured Power (cTDP)
Assured Power (cTDP) Assured Power (cTDP) Modes
Assured Power (cTDP) Modes
Intel® Memory Thermal Management
Processor Base Power Thermal and Power Specifications
Processor Line Thermal and Power Specifications
Error and Thermal Protection Signals
Thermal Sensor
Thermal Sensor Modes of Operation Temperature Trip Point Thermal Reporting to EC Thermal Trip Signal (SOCHOT#)
Modes of Operation
Temperature Trip Point
Thermal Reporting to EC
Thermal Trip Signal (SOCHOT#)
System Clocks
System Clocks Integrated Clock Controller (ICC) I/O Signal Pin States Clock Topology
Integrated Clock Controller (ICC)
Integrated Clock Controller (ICC) Signal Descriptions
Signal Descriptions
I/O Signal Pin States
Clock Topology
Clock Topology Integrated Reference Clock PLL
Integrated Reference Clock PLL
Real Time Clock (RTC)
Real Time Clock (RTC) Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Integrated System Memory
Integrated System Memory Integrated LPDDR5x Memory Integrated Memory Controller (IMC) Power Management Signal Description
Integrated LPDDR5x Memory
Integrated LPDDR5x Memory Integrated LPDDR5x System Memory Timing Support Memory Controller (MC) Technology Enhancements of Intel® Fast Memory Access (Intel® FMA) Data Scrambling DRAM Clock Generation DRAM Reference Voltage Generation Post Package Repair (PPR) Refresh Management (RFM)
Integrated LPDDR5x
System Memory Timing Support
System Memory Timing Support SAGV Points
SAGV Points
Memory Controller (MC)
Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
Data Scrambling
DRAM Clock Generation
DRAM Reference Voltage Generation
Post Package Repair (PPR)
Refresh Management (RFM)
Integrated Memory Controller (IMC) Power Management
Integrated Memory Controller (IMC) Power Management DRAM Power Management and Initialization DDR Electrical Power Gating Power Training Dynamic Voltage and Frequency Scaling (DVFS)
DRAM Power Management and Initialization
DRAM Power Management and Initialization Conditional Self-Refresh Dynamic Power-Down DRAM I/O Power Management
Conditional Self-Refresh
Dynamic Power-Down
DRAM I/O Power Management
DDR Electrical Power Gating
Power Training
Dynamic Voltage and Frequency Scaling (DVFS)
Signal Description
USB Type-C* Sub System
USB Type-C* Sub System General Capabilities USB™ 4 Router xHCI Controllers Display Interface USB Type-C Signals
General Capabilities
USB™ 4 Router
USB™ 4 Router USB 4 Host Router Implementation Capabilities
USB 4 Host Router Implementation Capabilities
xHCI Controllers
xHCI Controllers USB 3 Controllers
USB 3 Controllers
USB 3 Controllers Extensible Host Controller Interface (xHCI) PCIe Interface
Extensible Host Controller Interface (xHCI)
PCIe Interface
Display Interface
USB Type-C Signals
Universal Serial Bus (USB)
Universal Serial Bus (USB) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
eXtensible Host Controller Interface (xHCI) Controller
eXtensible Host Controller Interface (xHCI) Controller
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
PCI Express* (PCIe*)
PCI Express* (PCIe*) Functional Description Signal Description I/O Signal Planes and States PCI Express* Root Port Support Feature Details
Functional Description
Functional Description PCI Express* Power Management Port 80h Decode Separate Reference Clock with Independent SSC (SRIS) Advanced Error Reporting Single - Root I/O Virtualization (SR - IOV) PCI Express* Receiver Lane Polarity Inversion Precision Time Measurement (PTM)
PCI Express* Power Management
Port 80h Decode
Separate Reference Clock with Independent SSC (SRIS)
Advanced Error Reporting
Single - Root I/O Virtualization (SR - IOV)
PCI Express* Receiver Lane Polarity Inversion
Precision Time Measurement (PTM)
Signal Description
I/O Signal Planes and States
PCI Express* Root Port Support Feature Details
Graphics
Graphics Processor Graphics Platform Graphics Hardware Feature
Processor Graphics
Processor Graphics Media Support (Intel® QuickSync and Clear Video Technology HD) Graphics Core Cache
Media Support (Intel® QuickSync and Clear Video Technology HD)
Media Support (Intel® QuickSync and Clear Video Technology HD) Hardware Accelerated Video Decode Hardware Accelerated Video Encode Hardware Accelerated Video Processing Hardware Accelerated Transcoding
Hardware Accelerated Video Decode
Hardware Accelerated Video Encode
Hardware Accelerated Video Processing
Hardware Accelerated Transcoding
Graphics Core Cache
Platform Graphics Hardware Feature
Platform Graphics Hardware Feature Hybrid Graphics
Hybrid Graphics
Display
Display Display Technologies Support Display Interfaces Display Features
Display Technologies Support
Display Interfaces
Display Interfaces Digital Display Interface DDI Signals Digital Display Interface TCP Signals
Digital Display Interface DDI Signals
Digital Display Interface TCP Signals
Display Features
Display Features General Capabilities Multiple Display Configurations High-bandwidth Digital Content Protection (HDCP) DisplayPort* High-Definition Multimedia Interface (HDMI*) embedded DisplayPort* (eDP*) Integrated Audio
General Capabilities
Multiple Display Configurations
High-bandwidth Digital Content Protection (HDCP)
DisplayPort*
DisplayPort* Multi-Stream Transport (MST)
Multi-Stream Transport (MST)
High-Definition Multimedia Interface (HDMI*)
embedded DisplayPort* (eDP*)
Integrated Audio
Processor Sideband Signals
Processor Sideband Signals Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
General Purpose Input and Output
General Purpose Input and Output Functional Description Signal Description
Functional Description
Functional Description Interrupt / IRQ via GPIO Requirement Integrated Pull-ups and Pull-downs SCI / SMI# and NMI Timed GPIO GPIO Blink (BK) and Serial Blink (SBK) GPIO Ownership Native Function and TERM Bit Setting
Interrupt / IRQ via GPIO Requirement
Integrated Pull-ups and Pull-downs
SCI / SMI# and NMI
Timed GPIO
GPIO Blink (BK) and Serial Blink (SBK)
GPIO Ownership
Native Function and TERM Bit Setting
Signal Description
Interrupt Timer Subsystem (ITSS)
Interrupt Timer Subsystem (ITSS) Feature Overview Functional Description
Feature Overview
Functional Description
Functional Description 8254 Timers APIC Advanced Interrupt Controller High Precision Event Timer (HPET)
8254 Timers
8254 Timers Timer Programming Reading from Interval Timer
Timer Programming
Reading from Interval Timer
APIC Advanced Interrupt Controller
High Precision Event Timer (HPET)
High Precision Event Timer (HPET) Timer Accuracy Timer Off-load Periodic Versus Non-Periodic Modes Enabling the Timers Interrupt Levels
Timer Accuracy
Timer Off-load
Periodic Versus Non-Periodic Modes
Enabling the Timers
Interrupt Levels
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Protocols Overview DMA Controller Reset Power Management Interrupts Error Handling Programmable SDA Hold Time
Protocols Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Programmable SDA Hold Time
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Reset Power Management Interrupts
Reset
Power Management
Interrupts
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Gigabit Ethernet Controller
Gigabit Ethernet Controller Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description GbE PCI Bus Interface Error Events and Error Reporting Ethernet Interface PCI Power Management
GbE PCI Bus Interface
Error Events and Error Reporting
Ethernet Interface
PCI Power Management
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Connectivity Integrated (CNVi)
Connectivity Integrated (CNVi) Functional Description Signal Description Integrated Pull-ups and Pull-downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-ups and Pull-downs
I/O Signal Planes and States
Controller Link
Controller Link Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States External CL_RST# Pin Driven/Open-drained Mode Support
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
External CL_RST# Pin Driven/Open-drained Mode Support
Integrated Sensor Hub (ISH)
Integrated Sensor Hub (ISH) Features Functional Description Signal Description Integrated Pull-Ups and Pull-Down I/O Signal Planes and States
Features
ISH I2C Controllers ISH I3C Controllers ISH UART Controller ISH GSPI Controller ISH GPIOs
ISH I2C Controllers
ISH I3C Controllers
ISH UART Controller
ISH GSPI Controller
ISH GPIOs
Functional Description
Functional Description ISH Micro-Controller SRAM PCI Host Interface ISH IPC ISH Interrupt Handling via IOAPIC (Interrupt Controller)
ISH Micro-Controller
SRAM
PCI Host Interface
ISH IPC
ISH Interrupt Handling via IOAPIC (Interrupt Controller)
Signal Description
Integrated Pull-Ups and Pull-Down
I/O Signal Planes and States
System Management Interface and SMLink
System Management Interface and SMLink System Management Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
System Management
System Management Theory of Operation
Theory of Operation
Theory of Operation Handling an Intruder TCO Modes
Handling an Intruder
TCO Modes
Functional Description
Functional Description Integrated USB-C* Usage
Integrated USB-C* Usage
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
SPI0 for Flash SPI0 Support for TPM
SPI0 for Flash
SPI0 Support for TPM
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Enhanced Serial Peripheral Interface (eSPI)
Enhanced Serial Peripheral Interface (eSPI) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Operating Frequency Protocols WAIT States from eSPI Device In-Band Link Reset Device Discovery Flash Sharing Mode PECI Over eSPI Multiple OOB Processes Channels and Supported Transactions
Operating Frequency
Protocols
WAIT States from eSPI Device
In-Band Link Reset
Device Discovery
Flash Sharing Mode
PECI Over eSPI
Multiple OOB Processes
Channels and Supported Transactions
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial IO Generic SPI (GSPI) Controllers
Intel® Serial IO Generic SPI (GSPI) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Functional Description Controller Overview DMA Controller Reset Power Management Interrupts Error Handling
Controller Overview
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Touch Host Controller (THC)
Touch Host Controller (THC) Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
Functional Description
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers Functional Description Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States LSx
Functional Description
UART Serial (RS-232) Protocols Overview 16550 8-bit Addressing - Debug Driver Compatibility DMA Controller Reset Power Management Interrupts Error Handling
UART Serial (RS-232) Protocols Overview
16550 8-bit Addressing - Debug Driver Compatibility
DMA Controller
Reset
Power Management
Interrupts
Error Handling
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
LSx
LSx LSx Signal Description Integrated Pull-Ups and Pull-Downs I/O Signal Planes and States
LSx Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Private Configuration Space Port ID
Testability and Monitoring
Testability and Monitoring Signal Description I/O Signal Planes and States
Signal Description
I/O Signal Planes and States
Miscellaneous Signals
Signal Description Integrated Pull-Ups and Pull-Downs Ground and Reserved Signals
Signal Description
Integrated Pull-Ups and Pull-Downs
Ground and Reserved Signals

DMA Controller

The I2C controllers 0 to 3 (I2C0 - I2C3) each has an integrated DMA controller. The I2C controller 4 and 5 (I2C4 and I2C5) only implement the I2C host controllers and do not incorporate a DMA. Therefore, I2C4 and I2C5 are restricted to operate in PIO mode only.

DMA Transfer and Setup Modes

The DMA can operate in the following modes:

  1. Memory to peripheral transfers. This mode requires the peripheral to control the flow of the data to itself.
  2. Peripheral to memory transfer. This mode requires the peripheral to control the flow of the data from itself.

The DMA supports the following modes for programming:

  1. Direct programming. Direct register writes to DMA registers to configure and initiate the transfer.
  2. Descriptor based linked list. The descriptors will be stored in memory (such as DDR or SRAM). The DMA will be informed with the location information of the descriptor. DMA initiates reads and programs its own register. The descriptors can form a linked list for multiple blocks to be programmed.
  3. Scatter Gather mode.

Channel Control

  • The source transfer width and destination transfer width is programmable. The width can be programmed to 1, 2, or 4 bytes.
  • Burst size is configurable per channel for source and destination. The number is a power of 2 and can vary between 1,2,4,...,128. This number times the transaction width gives the number of bytes that will be transferred per burst.
  • Individual channel enables. If the channel is not being used, then it should be clock gated.
  • Programmable Block size and Packing/Unpacking. Block size of the transfer is programmable in bytes. Block size is not limited by the source or destination transfer widths.
  • Address incrementing modes: The DMA has a configurable mechanism for computing the source and destination addresses for the next transfer within the current block. The DMA supports incrementing addresses and constant addresses.
  • Flexibility to configure any hardware handshake sideband interface to any of the DMA channels.
  • Early termination of a transfer on a particular channel.
Reset