Intel® Core™ Ultra 200V Series Processors
Datasheet, Volume 1 of 2
Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)
Intel® VT-d Objectives
The key Intel® VT-d objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Intel® VT-d provides accelerated I/O performance for a Virtualization platform and provides software with the following capabilities:
- I/O Device Assignment and Security: for flexibly assigning I/O devices to VMs and extending the protection and isolation properties of VMs for I/O operations.
- DMA Remapping: for supporting independent address translations for Direct Memory Accesses (DMA) from devices.
- Interrupt Remapping: for supporting isolation and routing of interrupts from devices and external interrupt controllers to appropriate VMs.
- Reliability: for recording and reporting to system software DMA and interrupt errors that may otherwise corrupt memory or impact VM isolation.
Intel® VT-d accomplishes address translation by associating transaction from a given I/O device to a translation table associated with the Guest to which the device is assigned. It does this by means of the data structure in the following illustration. This table creates an association between the device's PCI Express* Bus/Device/Function (B/D/F) number and the base address of a translation table. This data structure is populated by a VMM to map devices to translation tables in accordance with the device assignment restrictions above and to include a multi-level translation table (VT-d Table) that contains Guest specific address translations.
Device to Domain Mapping Structure in Legacy Mode
Device to Domain Mapping Structure in Scalable Mode
Intel® VT-d functionality often referred to as an Intel® VT-d Engine, has typically been implemented at or near a PCI Express* host bridge component of a computer system. This might be in a chipset component or in the PCI Express functionality of a processor with integrated I/O. When one such VT-d engine receives a PCI Express transaction from a PCI Express bus, it uses the B/D/F number associated with the transaction to search for an Intel® VT-d translation table. In doing so, it uses the B/D/F number to traverse the data structure shown in the above figure.
- If it finds a valid Intel® VT-d table in this data structure, it uses that table to translate the address provided on the PCI Express bus.
- If it does not find a valid translation table for a given translation, this results in an Intel® VT-d fault.
If Intel® VT-d translation is required, the Intel® VT-d engine performs an N-level table walk.
http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf
Intel® VT-d Key Features
The processor supports the following Intel® VT-d features:
- Memory controller and processor graphics comply with the Intel® VT-d 4.0 Specification.
- Intel® Core™ Ultra 200V Series Processor has 3 Intel® VT-d DMA Remapping Hardware Units:
- 42-bit guest physical address and host physical address widths
- 4-level Intel® VT-d Page walk - all VTd engines support 4-level tables only (adjusted guest address width of 48 bits)
- Support Device-TLB for both engines for integrated accelerators (that is, GFX and Non-GFX)
- Support for register-based fault recording only (for single entry only) and support for MSI interrupts for faults
- Support for both leaf and non-leaf caching
- Support for non-caching of invalid page table entries
- Support for hardware-based flushing of translated but pending writes and pending reads, upon invalidation
- Support for all Queue based Invalidation descriptor types
- Support for Interrupt Remapping and Posted Interrupt
- Support Abort DMA Mode
- Support Performance Monitoring
- Intel® VT-d - All VTd engines support 4K, 2M and 1G page sizes
- Scalable Mode - All VTd engines support Scalable mode operation (using RID_PASID only)
- Nested - All Intel® VT-d engines support Nested translation