Intel® Core™ Ultra 200V Series Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 829568 | 05/27/2025 | 004 | Confidential |
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| PCIE_1_TX_N/GbE_TX_N PCIE_1_TX_P/GbE_TX_P | O | Differential transmit pairs to the Intel® Ethernet Connection I219 based on the PCIe interface. Refer to PCI Express* (PCIe*) for details on the PCI Express*transmit signals. |
| PCIE_1_RX_N/GbE_RX_N PCIE_1_RX_P/GbE_RX_P | I | Differential receive pairs to the Intel® Ethernet Connection I219 based on the PCIe interface. Refer to PCI Express* (PCIe*) for details on the PCI Express* transmit signals. |
| GPP_C04/SML0DATA/USB-C_GPP_C04 | I/OD | System Management Link data signal interface to Intel® Ethernet Connection I219. Refer to System Management Interface and SMLink for details on the SML0DATA signal. |
| GPP_C03/SML0CLK/USB-C_GPP_C03 | I/OD | System Management Link data signal interface to Intel® Ethernet Connection I219. Refer to System Management Interface and SMLink for details on the SML0CLK signal. |
| GPP_V10/LANPHYPC | O | LAN PHY Power Control: LANPHYPC should be connected to LAN_DISABLE_N on the PHY. Processor will drive LANPHYPC low to put the PHY into a low power state when functionality is not needed. |
| GPP_V11/SLP_LAN# | IO | LAN Sub-System Sleep Control: If the Gigabit Ethernet Controller is enabled, when SLP_LAN# is de-asserted it indicates that the PHY device must be powered. When SLP_LAN# is asserted, power can be shut off to the PHY device. |
| GPP_V02/SOC_WAKE# | I | SOC_WAKE: LAN Wake Indicator from the GbE PHY. |