Intel® Core™ Ultra 200V Series Processors
Datasheet, Volume 1 of 2
Terminology and Special Marks
Terminology Usage
This document uses the term Processor to indicate the Compute Tile + SOC Tile. Individually, Compute Tile and SOC Tile is used.
| Term | Description | ||
|---|---|---|---|
| 4K | Ultra High Definition (UHD) | ||
| AES | Advanced Encryption Standard | ||
| AGC | Adaptive Gain Control | ||
| API | Application Programming Interface | ||
| AVC | Advanced Video Coding | ||
| BLT | Block Level Transfer | ||
| BPP | Bits per Pixel | ||
| CDR | Clock and Data Recovery | ||
| CTLE | Continuous Time Linear Equalizer | ||
| D0ix-states | USB controller power states ranging from D0i0 to D0i3, where D0i0 is fully powered on and D0i3 is primarily powered off. Controlled by SW. | ||
| DDC | Digital Display Channel | ||
| DDI | Digital Display Interface for DisplayPort or HDMI/DVI | ||
| DFE | Decision Feedback Equalizer | ||
| DMA | Direct Memory Access | ||
| DPPM | Dynamic Power Performance Management | ||
| DP* | DisplayPort* | ||
| DSC | Display Stream Compression | ||
| DTS | Digital Thermal Sensor | ||
| eDP* | Embedded DisplayPort* | ||
| EU | Execution Unit in the Graphics Processor | ||
| GSA | Graphics in System Agent | ||
| HDCP | High-Bandwidth Digital Content Protection | ||
| HDMI* | High Definition Multimedia Interface | ||
| IMC | Integrated Memory Controller | ||
| Intel® 64 Technology | 64-bit memory extensions to the IA-32 architecture | ||
| Intel® DPST | Intel® Display Power Saving Technology | ||
| Intel® PTT | Intel® Platform Trust Technology | ||
| Intel® TXT | Intel® Trusted Execution Technology | ||
| Intel® VT | Intel® Virtualization Technology. Processor Virtualization, when used in conjunction with Virtual Machine Monitor software, enables multiple, robust independent software environments inside a single platform. | ||
| Intel® VT-d | Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel® VT-d is a hardware assist, under system software (Virtual Machine Manager or OS) control, for enabling I/O device Virtualization. Intel® VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel® VT-d. | ||
| Intel® TH | Intel® Trace Hub | ||
| IOV | I/O Virtualization | ||
| IPU | Image Processing Unit | ||
| LFM | Low Frequency Mode. corresponding to the Enhanced Intel SpeedStep® Technology’s lowest voltage/frequency pair. It can be read at MSR CEh [47:40]. | ||
| LLC | Last Level Cache | ||
| LPDDR5x | Fifth generation Low Power Double Data Rate SDRAM memory technology, x- high frequency. | ||
| LPSP | Low-Power Single Pipe | ||
| LSF | Lowest Supported Frequency.This frequency is the lowest frequency where manufacturing confirms logical functionality under the set of operating conditions. | ||
| LTR | The Latency Tolerance Reporting (LTR) mechanism enables Endpoints to report their service latency requirements for Memory Reads and Writes to the Root Complex, so that power management policies for central platform resources (such as main memory, RC internal interconnects, and snoop resources) can be implemented to consider Endpoint service requirements. | ||
| MFM | Minimum Frequency Mode. MFM is the minimum ratio supported by the processor and can be read from MSR CEh [55:48]. | ||
| MLC | Mid-Level Cache | ||
| MoP | Memory on Package | ||
| MPEG | Motion Picture Expert Group, international standard body JTC1/SC29/WG11 under ISO/IEC that has defined audio and video compression standards such as MPEG-1, MPEG-2, and MPEG-4, etc. | ||
| NCTF | Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved balls/lands, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. | ||
| PECI | Platform Environment Control Interface | ||
| PEG | PCI Express* Graphics | ||
| PL1, PL2, PL3, PL4 | Power Limit 1, Power Limit 2, Power Limit 3, Power Limit 4 | ||
| PMIC | Power Management Integrated Circuit | ||
| Processor | The 64-bit multi-core component (package) | ||
| Processor Core | The term “processor core” refers to the Si tile itself, which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the LLC. P core - performance cores, and LP E-core- efficiency cores. | ||
| Processor Graphics | Intel® Processor Graphics | ||
| PSR | Panel Self-Refresh | ||
| PSx | Voltage regulator power states (PS0, PS1, PS2) | ||
| S0ix-states | Processor residency idle standby power states. | ||
| SCI | System Control Interrupt. SCI is used in the ACPI protocol. | ||
| SDP | Scenario Design Power | ||
| SVID | Serial Voltage IDentification Code HW and SW protocol used by CPU to dynamically control a variable Voltage regulator | ||
| SHA | Secure Hash Algorithm | ||
| SSC | Spread Spectrum Clock | ||
| TAC | Thermal Averaging Constant | ||
| T&L | Thin and Light | ||
| TBT | Thunderbolt™ Interface | ||
| TCC | Thermal Control Circuit | ||
| TDP | Processor Base Power | ||
| TTV Processor Base Power | Thermal Test Vehicle Processor Base Power | ||
| VCC_PCORE, VCC_ECORE, VCCL2 | Processor Core Power Supply | ||
| VCCGT | Processor Graphics Power Supply | ||
| VCCSA | System Agent Power Supply | ||
| VLD | Variable Length Decoding | ||
| VPID | Virtual Processor ID | ||
| VSS | Processor Ground |
| Mark | Definition |
|---|---|
| [] | Brackets ([]) sometimes follow a ball, pin, registers or a bit name. These brackets enclose a range of numbers, for example, TCP[2:0]_TXRX_P[1:0] may refer to four USB-C* pins or EAX[7:0] may indicate a range that is 8 bits length. |
| # | A suffix of # indicates an active low signal. For example, CATERR# _N does not refer to a differential pair of signals such as CLK_P, CLK_N |
| h | Hexadecimal numbers are identified with an h in the number. All numbers are decimal (base 10) unless otherwise specified. Non-obvious binary numbers have the ‘b’ enclosed at the end of the number. For example, 0101b |