DRAM Power Management and Initialization

The processor implements extensive support for power management on the memory interface.

The DRAM Powerdown is one of the power-saving means. When DRAM is in Powerdown state, the internal DDR clock is disabled and the DDR power is reduced. The power-saving differs according to the selected mode.

The processor supports our different types of power-down modes in package C0 state. The different power-down modes can be enabled through BIOS configuration.

The different power-down modes supported are:

• No power-down
• Active Power-down (APD): This mode is entered if there are open pages entering power down state. In this mode the open pages are retained. Power-saving in this mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this mode is fined by tXP.
• Pre-charged Power-down (PPD): This mode is entered if all banks in DDR are pre-charged when entering Powerdown state. Power-saving in this mode is intermediate – better than APD. Power consumption is defined by IDD2P. Exiting this mode is defined by tXP. The difference from APD mode is that when waking-up, all page-buffers are empty.)

The Powerdown state is determined per rank, whenever it is inactive. Each rank has an idle counter. The idle-counter starts counting as soon as the rank has no accesses, and if it expires, the rank may enter power-down while no new transactions to the rank arrive to queues. It is important to understand that since the power-down decision is per rank, the IMC can find many opportunities to power down ranks, even while running memory intensive applications; the savings are significant. This is significant when each channel is populated with more ranks.

• Opportunistic Self refresh (SR): This mode is entered if all channels in the IMC are idle. The idle-counter begins counting at the last incoming transaction arrival and once the counter expires and the IMC completed all the transactions it will put the DRAM in self refresh state. Exiting this mode is defined by tXSR