PCI Express* Root Port Support Feature Details

Intel® Core™ Ultra 200V Series Processors

ID	Date	Version	Classification
829568	05/27/2025	004	Confidential

Product	Max Transfer Rate	Max Devices (Root Ports)	Max Lanes	PCIe Gen Type	Encoding	Transfer Rate (MT/s)	Theoretical Max Bandwidth (GB/s)
Product	Max Transfer Rate	Max Devices (Root Ports)	Max Lanes	PCIe Gen Type	Encoding	Transfer Rate (MT/s)	x1	x2	x4
Intel^® Core™ Ultra 200V Series Processor	32 GT/s (Gen5)	6	8	1	8b/10b	2500	0.25	0.50	1.00
				2	8b/10b	5000	0.50	1.00	2.00
				3	128b/130b	8000	1.00	2.00	3.94
				4	128b/130b	16000	1.97	3.94	7.88
				5	128b/130b	32000	3.94	7.88	15.75
Notes: Theoretical Maximum Bandwidth (GB/s) = ((Transfer Rate * Encoding * # PCIe Lanes) /8)/1000 Gen4 with 4 PCIe Lanes Example: = ((16000 * 128/130* 4)/8)/1000 = 7.88 GB/s Gen5 with 4 PCIe Lanes Example: = ((32000 * 128/130* 4)/8)/1000 = 15.75 GB/s When GbE is enabled on a PCIe* Root Port, the Max. Device (Root Ports) value listed is reduced by a factor of 1

Notes:

Device (BDF) groupings have multiple functions, the lowest active Root Port within the Device (BDF) grouping will always be assigned Function 0 while any remaining active Root Port within the Device (BDF) grouping will be assigned their mapped Function # as shown.

Reduced Root Port width configurations, within Bi-Furcation configurations, are supported (example: x2 PCIe End Point Device populated in a PCIe Controller set as 1px4 will result in a 1px2 PCIe Root Port configuration or x1 PCIe End Point Device populated in a PCIe Controller set as 1px4 will result in a 1px1 PCIe Root Port configuration).

PCIe Gen5 Controller hardware and Gen5 PHY’s will be validated and certified by Intel. Full support is pending on PCIe Gen5 third party vendor ecosystem readiness, device availability, and interoperability testing.

The PCIe* Link Configuration support will vary depending on the SKU. Refer to the SKU details covered in the "Introduction" section

PCIe Configuration (#p) x (#) = (Number of PCIe Root Ports) x (Number of Data Lane Pairs per PCIe Root Port)

RP# refers to a specific PCI Express* Root Port #; for example RP3 = PCI Express* Root Port 3

A PCIe* Lane is composed of a single pair of Transmit (TX) and Receive (RX) differential pairs. A connection between two PCIe* devices is known as a PCIe* Link, and is built up from a collection of one or more PCIe* Lanes which make up the width of the link (such as bundling 2 PCIe* Lanes together would make a x2 PCIe* Link). A PCIe* Link is addressed by the lowest number PCIe* Lane it connects to and is known as the PCIe* Root Port (such as a x2 PCIe* Link connected to PCIe* Lanes 3 and 4 would be called x2 PCIe* Root Port 3).

The PCIe* Lanes can be configured independently from one another but the max number of configured Root Ports (Devices) must not be exceeded

Unidentified lanes within a PCIe* Link Configuration are disabled but their physical lanes are used for the identified Root Port