Intel® Core™ Ultra 200V Series Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 829568 | 05/27/2025 | 004 | Confidential |
Functional Description
| PCIe Controller Feature | Intel® Core™ Ultra 200V Series Processor Controllers | |
|---|---|---|
| 1 | 2 | |
| L1 Sub-States (L1.0, L1.1, L1.2) | Yes | Yes |
| L0s Link State (RX/TX) | Yes | Yes |
| S4/S5 Sleep States (Sx) | Yes | Yes |
| Common Clock Mode | Yes | Yes |
| Separate Reference Clock with Independent SSC (SRIS) | Yes | No |
| Separate Reference Clock with No SSC (SRNS) | Yes | No |
| Precision Time Management (PTM) | Yes | Yes |
| Advanced Error Reporting (AER) | Yes | Yes |
| End-to-End Lane Reversal | Yes | Yes |
| Latency Tolerance Reporting (LTR) | Yes | Yes |
| PCIe TX Half Swing | No | No |
| PCIe TX Full Swing | Yes | Yes |
| Run Time D3 (RTD3) | Yes | Yes |
| RTD3 through PFET_EN | Yes | Yes |
| Access Control Services (ACS) | Yes | Yes |
| Alternative Routing-ID Interpretation (ARI) | Yes | Yes |
| Port 80h Decode | Yes | Yes |
| Lane Polarity Inversion | Yes | Yes |
| PCIe Controller Root Port Hot-Plug Connector Hot-Plug via CLKREQ# | Yes | Yes |
| Downstream Port Containment (DPC) | No | No |
| Enhanced Downstream Port Containment (eDPC) | No | No |
| Virtual Channel (VC) | VC0 | VC0 |
| NVMe Cycle Router | No | No |
| Volume Management Device (Intel® VMD) | No | No |
| RAID[0] and RAID[1] Mode Support 1 | No | No |
| RAID[5] and RAID[10] Mode Support 2 | No | No |
| Mammoth Glacier Discrete Device Support (M.2 1px2, 1px4) | Yes | Yes |
| Hybrid Dual Port Module Support (M.2 2px2) | Yes | No |
| PCIe Controller (PC) Root Port (RP) Peer-2-Peer (P2P) Mem Write Transactions | RPs within PC1 or within PC2 = Yes RPs between PC1 and PC2 = Yes | |
| PCIe Controller (PC) Root Port (RP) Peer-2-Peer (P2P) Mem Read Transactions | No | |
| PCIe Controller (PC) Root Port (RP) Peer-2-Peer (P2P) MCTP VDM Transactions | RPs within PC1 or within PC2 = Yes RPs between PC1 and PC2 = Yes | |
| PCIe Root Port Initiated Dynamic Width Change | No | No |
| PCIe Root Port Initiated Dynamic Speed Change | Yes | Yes |
| End Point Device Initiated Dynamic Width Change | Yes | Yes |
| End Point Device Initiated Dynamic Speed Change | Yes | Yes |
| Flattening Portal Bridge (FPB) | No | No |
- No restrictions on PCIe Controller. PCIe RAID is expected to work across all Root Ports within a PCIe Controller and between Root Ports from different PCIe Controllers.
- The Intel® Rapid Storage Technology (RST) does not restrict RAID modes so if any unsupported RAID mode is enabled it is up to the motherboard designer to validate any non-supported RAID mode.