Processor P/LP E Core C-State Rules

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The following are general rules for all processor P/LP E core C-states unless specified otherwise:

A processor P/LP E core C-State is determined by the lowest numerical thread state (such as Thread 0 requests C1E while Thread 1 requests C6 state, resulting in a processor P/LP E core C1E state). Refer to the G, S, and C Interface State Combinations table.
A processor P/LP E core transitions to C0 state when:
- An interrupt occurs
- There is an access to the monitored address if the state was entered using an MWAIT/Timed MWAIT instruction
- The deadline corresponding to the Timed MWAIT instruction expires
An interrupt directed toward a single thread wakes up only that thread.
If any thread in a processor P/LP E core is active (in C0 state), the core’s C-state will resolve to C0.
Any interrupt coming into the processor package may wake any processor P/LP E core.
A system reset re-initializes all processor P/LP E cores.

Core C-states

Core C-State	C-State Request Instruction	Description
C0	N/A	The normal operating state of a processor P/LP E core where a code is being executed
C1	MWAIT(C1)	AutoHalt - core execution stopped, autonomous clock gating (package in C0 state)
C1E	MWAIT(C1E)	Core C1 + lowest frequency and voltage operating point (package in C0 state)
C6-C10	MWAIT(C6/10) or IO read=P_LVL3//6/8	Processor P/LP E, flush their L1 instruction cache, the L1 data cache, and L2 cache to the LLC shared cache cores save their architectural state to an SRAM before reducing P/LP E cores voltage, if possible may also be reduced to 0V. Core clocks are off.

This feature is disabled by default. BIOS should enable it in the PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by this register.

Package C-States

Requesting the Low-Power Idle States Package C-States