SPI0 Support for TPM

The processor SPI0 flash controller supports a discrete TPM on the platform via its dedicated SPI0_​CS2# signal. The platform must have no more than 1 TPM.

SPI0 controller supports accesses to SPI0 TPM at approximately 17 MHz, 33 MHz and 48 MHz depending on the soft strap. 20 MHz is the reset default, a valid soft strap setting overrides the requirement for the 20 MHz. SPI0 TPM device must support a clock of 20 MHz, and thus should handle 15-20 MHz. It may but is not required to support a frequency greater than 20 MHz.

TPM requires the support for the interrupt routing. However, the TPM’s interrupt pin is routed to the processor's a interrupt configurable GPIO pin. Thus, TPM interrupt is completely independent from the SPI0 controller.