Intel® Core™ Ultra 200V Series Processors
Datasheet, Volume 1 of 2
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| Intel® High Definition Audio Signals | ||
| GPP_D17/HDA_RST#/DMIC_DATA1/USB-C_GPP_D17 | O | Intel HD Audio Reset: Host H/W reset to internal and external codecs. |
| GPP_D11/HDA_SYNC/DMIC_CLK_B1/USB-C_GPP_D11 | O | Intel HD Audio Sync: 48 kHz fixed rate frame sync to the codecs. |
| GPP_D10/HDA_BCLK/DMIC_CLK_A1/USB-C_GPP_D10 | O | Intel HD Audio Bit Clock: Up to 24 MHz serial data clock generated by the Intel® HD Audio controller. |
| GPP_D12/HDA_SDO/USB-C_GPP_D12 | O | Intel HD Audio Serial Data Out: Serial TDM data output to the codecs. The serial output is double-pumped for a bit rate of up to 48 Mb/s. |
| GPP_D13/HDA_SDI0/USB-C_GPP_D13 | I/O | Intel HD Audio Serial Data In 0: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
| GPP_D16/HDA_SDI1/DMIC_CLK_B0/USB-C_GPP_D16 | I/O | Intel HD Audio Serial Data In 1: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. |
| DMIC Interface | ||
| GPP_S02/SNDW1_CLK/SNDW0_DATA1/DMIC_CLK_A0 or GPP_D14/DMIC_CLK_A0/USB-C_GPP_D14 | O | Digital Mic Clock A0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance A) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance A) should be used. |
| GPP_S06/SNDW3_CLK/DMIC_CLK_A1 or GPP_D10/HDA_BCLK/DMIC_CLK_A1/USB-C_GPP_D10 | O | Digital Mic Clock A1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance A) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance A) should be used. |
| GPP_S04/SNDW2_CLK/SNDW0_DATA3/DMIC_CLK_B0 or GPP_D16/HDA_SDI1/DMIC_CLK_B0/USB-C_GPP_D16 | O | Digital Mic Clock B0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance B) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance B) can be disconnected. |
| GPP_S05/SNDW2_DATA/DMIC_CLK_B1 or GPP_D11/HDA_SYNC/DMIC_CLK_B1/USB-C_GPP_D11 | O | Digital Mic Clock B1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance B) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance B) can be disconnected. |
| GPP_S03/SNDW1_DATA/SNDW0_DATA2/DMIC_DATA0 or GPP_D15/DMIC_DATA0/USB-C_GPP_D15 | I | Digital Mic Data:Serial data input from the digital mic. |
| GPP_S07/SNDW3_DATA/DMIC_DATA1 or GPP_D17/HDA_RST#/DMIC_DATA1/USB-C_GPP_D17 | I | Digital Mic Data:Serial data input from the digital mic. |
| SoundWire Interface | ||
| GPP_S00/SNDW0_CLK | I/O | SoundWire Clock: Serial bit clock used to control the timing of a transfer. |
| GPP_S01/SNDW0_DATA0 | I/O | SoundWire Data: Serialized data line containing framing and data being transmitted/received. |
| GPP_S02/SNDW1_CLK/SNDW0_DATA1/DMIC_CLK_A0 | I/O | SoundWire Clock: Serial bit clock used to control the timing of a transfer. SoundWire Data: Serialized data line containing framing and data being transmitted/received. |
| GPP_S03/SNDW1_DATA/SNDW0_DATA2/DMIC_DATA0 | I/O | SoundWire Data: Serialized data line containing framing and data being transmitted/received. |
| GPP_S04/SNDW2_CLK/SNDW0_DATA3/DMIC_CLK_B0 | I/O | SoundWire Clock: Serial bit clock used to control the timing of a transfer. SoundWire Data: Serialized data line containing framing and data being transmitted / received. |
| GPP_S05/SNDW2_DATA/DMIC_CLK_B1 | I/O | SoundWire Data: Serialized data line containing framing and data being transmitted / received. |
| GPP_S06/SNDW3_CLK/DMIC_CLK_A1 | I/O | SoundWire Clock: Serial bit clock used to control the timing of a transfer. |
| GPP_S07/SNDW3_DATA/DMIC_DATA1 | I/O | SoundWire Data: Serialized data line containing framing and data being transmitted / received. |
| SNDW_RCOMP | A | SoundWire Resistor compensation. |