GPP_​V01/ACPRESENT

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ACPRESENT: This input pin indicates when the platform is plugged into AC power or not.

GPP_​V00/BATLOW#

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Battery Low: An input from the battery to indicate that there is insufficient power to boot the system. Assertion will prevent wake from S4/S5 states. This signal can also be enabled to cause an SMI# when asserted.

GPP_​V10/LANPHYPC

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LAN PHY Power Control: LANPHYPC is used to indicate that power needs to be restored to the Platform LAN Connect Device.

PLT_​PWROK

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PLT Power OK: When asserted, it is an indication to the processor that all of its core power rails have been stable. The platform may drive asynchronously. For PLTRST# to be de-asserted PLT_​PWROK must be asserted first - one of the conditions for PLTRST# de-assertion

GPP_​B13/PLTRST#/USB-C_​GPP_​B13

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Platform Reset: The processor asserts PLTRST# to reset deviceson the platform. The processor asserts PLTRST# low in Sx states and when a cold, warm, or global reset occurs. The processor de-asserts PLTRST# upon exit from Sx states and the forementioned resets. There is no guaranteed minimum assertion time for PLTRST#.

GPP_​E21/PMCALERT#/USB-C_​GPP_​E21

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PMC Alert Pin: Supports USB-C* PD controller architecture.

GPP_​V03/PWRBTN#

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Power Button: The Power Button may cause an SMI# or SCI to indicate a system request to go to a sleep state. If the system is already in a sleep state, this signal will cause a wake event. If PWRBTN# is pressed for more than 4 seconds (default; timing is configurable), this will cause an unconditional transition (power button override) to the S5 state. Override will occur even if the system is in the S4 states. This signal has an internal Pull-up resistor and has an internal 16 ms de-bounce on the input.

RSMRST#

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Primary Well Reset: This signal is used for resetting the primary power plane logic. This signal must be asserted for at least 10ms before de-asserting.

GPP_​V06/SLP_​A#

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SLP_​A#: Signal asserted when the Intel^® CSME platform goes to M-Off or M3-PG. Depending on the platform, this pin may be used to control power to various devices that are part of the Intel^® CSME sub-system in the platform. If you are not using SLP_​A# for any functional purposes on your platform, or can tolerate lack of minimum assertion time, program the "SLP_​A# minimum assertion width" value to the minimum.

SLP_​A# functionality can be utilized on the platform via either the physical pin or via the SLP_​A# virtual wire over eSPI.

GPP_​V11/SLP_​LAN#

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LAN Sub-System Sleep Control: When SLP_​LAN# is de-asserted it indicates that the Platform LAN Connect Device must be powered. When SLP_​LAN# is asserted, power can be shut off to the Platform LAN Connect Device. SLP_​LAN# will always be de-asserted in S0 and anytime SLP_​A# is de-asserted.

GPP_​V08/SLP_​WLAN#

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WLAN Sub-System Sleep Control: When SLP_​WLAN# is asserted, power can be shut off to the external wireless LAN device. SLP_​WLAN# will always will be de-asserted in S0. If you are not using SLP_​WLAN# for any functional purposes on your platform, or can tolerate lack of minimum assertion time, program the "SLP_​A# minimum assertion width" value to the minimum.

GPP_​V04/SLP_​S3#

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S3 Sleep Control:SLP_​S3# is for power plane control. This signal shuts off power to all non-critical systems when in the S4 or S5 state.

GPP_​V05/SLP_​S4#

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S4 Sleep Control: SLP_​S4# is for power plane control. This signal shuts power to all non-critical systems when in the S4 or S5 state.

GPP_​V09/SLP_​S5#

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S5 Sleep Control: SLP_​S5# is for power plane control. This signal is used to shut power off to all non-critical systems when in the S5 state.

GPP_​V07/SUSCLK

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Suspend Clock: This clock is a digitally buffered version of the RTC clock.

GPP_​A02/ESPI_​IO2/PRIMPWRDNACK/USB-C_​GPP_​A02

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PRIMPWRDNACK: Active high. Asserted by the processor on behalf of the Intel^® CSME when it does not require the processor Primary well to be powered.

GPP_​F09/SX_​EXIT_​HOLDOFF#/ISH_​GP11/USB-C_​GPP_​F09

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Sx Exit Holdoff Delay: Delay exit from Sx state after SLP_​A# is de-asserted. Note:When eSPI is enabled, the flash sharing functionality using SX_​EXIT_​HOLDOFF# is not supported, but the pin still functions to hold off Sx exit after SLP_​A# de-assertion.

SYS_​RESET#

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System Reset: This pin forces an internal reset after being de-bounced.

GPP_​E02/PROC_​GP3/VRALERT#/ISH_​GP10/USB-C_​GPP_​E02

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VR Alert: ICC Max throttling indicator from the processor voltage regulators. VRALERT# pin allows the VR to force processor throttling to prevent an over current shutdown. PMC based on the VRALERT# and messages from the processor. The messages from the processor allows the processor to constrain the processor to a particular power budget.

GPP_​V12/WAKE#

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PCI Express* Wake Event in Sx: Input Pin in Sx. Sideband wake signal on PCI Express* asserted by components requesting wake up.

EPD_​ON_​IN

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Input signal to compute, this signal should be shorted with EPD_​ON_​OUT on the platform Level for test issue

EPD_​ON_​OUT

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Output signal from SOC tile, this signal should be shorted with EPD_​ON_​IN on the platform Level for test issue

GPP_​B12/SLP_​S0#/USB-C_​GPP_​B12

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S0 Sleep Control: When the processor is in C10 state, this pin will assert to indicate VR controller can go into a light load mode. This signal can also be connected to EC for other power management related optimizations.

SYS_​PWROK

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System Power OK: This generic power good input to the processor is driven and utilized in a platform-specific manner. While PLT_​PWROK always indicates that the core wells of the processor are stable, SYS_​PWROK is used to inform the processor that some other system component(s) power rails are stable, and the system is ready to start the exit from reset.

VCCST_​EN

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Output signal from SOC tile to turn on the VCCST rail

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When asserted, PROC_​C10_​GATE# is the indication to the system that the processor is entering C10.

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Time Synchronization: Used for synchronization both input (latch time when pin asserted) and output (toggle pin when programmed time is hit).