Handling an Intruder

Legal Disclaimer
Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
Memory Mapping
- Functional Description
- Memory Map
  - Boot Block Update Scheme
Security Technologies
Intel® Virtualization Technology (Intel® VT)
Instructions Set Enhancements
Intel® Image Processing Unit (Intel® IPU7)
Intel® Neural Processing Unit (Intel® NPU)
- Functional Description
  - HOST Control
  - Deep Learning Accelerators (NCE)
Audio Voice and Speech
Power Management
Power Delivery
Electrical Specifications
Thermal Management
System Clocks
Real Time Clock (RTC)
- Signal Description
- I/O Signal Planes and States
Integrated System Memory
USB Type-C* Sub System
Universal Serial Bus (USB)
PCI Express* (PCIe*)
Graphics
- Processor Graphics
  - Media Support (Intel® QuickSync and Clear Video Technology HD)
  - Graphics Core Cache
- Platform Graphics Hardware Feature
  - Hybrid Graphics
Display
Processor Sideband Signals
General Purpose Input and Output
- Functional Description
- Signal Description
Interrupt Timer Subsystem (ITSS)
- Feature Overview
- Functional Description
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Gigabit Ethernet Controller
Connectivity Integrated (CNVi)
Controller Link
Integrated Sensor Hub (ISH)
System Management Interface and SMLink
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Private Configuration Space Port ID
Testability and Monitoring
- Signal Description
- I/O Signal Planes and States
Miscellaneous Signals

The Processor has an input signal, INTRUDER#, that can be attached to a switch that is activated when the system’s case is open. This input has a two RTC clock debounce. If INTRUDER# goes active (after the debouncer), this will set the INTRD_DET bit in the TCO2_STS register. The INTRD_SEL bits in the TCO_CNT register can enable the Processor to cause an SMI# or interrupt. The BIOS or interrupt handler can then cause a transition to the S5 state by writing to the SLP_EN bit.

The software can also directly read the status of the INTRUDER# signal (high or low) by clearing and then reading the INTRD_DET bit. This allows the signal to be used as a GPIO if the intruder function is not required.

If the INTRUDER# signal goes inactive some point after the INTRD_DET bit is written as a 1, then the INTRD_DET bit will go to a 0 when INTRUDER# input signal goes inactive.

Note:This is slightly different than a classic sticky bit, since most sticky bits would remain active indefinitely when the signal goes active and would immediately go inactive when a 1 is written to the bit.

TCO Modes

Theory of Operation TCO Modes