Intel® Core™ Ultra 200V Series Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 829568 | 05/27/2025 | 004 | Confidential |
Legal Disclaimer
Revision History
Introduction
Processor and Device IDs
Package Mechanical Specifications
Memory Mapping
Security Technologies
Intel® Virtualization Technology (Intel® VT)
Instructions Set Enhancements
Intel® Image Processing Unit (Intel® IPU7)
Intel® Neural Processing Unit (Intel® NPU)
Audio Voice and Speech
Power Management
Power Delivery
Electrical Specifications
Thermal Management
System Clocks
Real Time Clock (RTC)
Integrated System Memory
USB Type-C* Sub System
Universal Serial Bus (USB)
PCI Express* (PCIe*)
Graphics
Display
Processor Sideband Signals
General Purpose Input and Output
Interrupt Timer Subsystem (ITSS)
Intel® Serial I/O Inter-Integrated Circuit (I2C) Controllers
Intel® Serial I/O Improved Inter-Integrated Circuit (I3C) Controllers
Gigabit Ethernet Controller
Connectivity Integrated (CNVi)
Controller Link
Integrated Sensor Hub (ISH)
System Management Interface and SMLink
Serial Peripheral Interface (SPI)
Enhanced Serial Peripheral Interface (eSPI)
Intel® Serial IO Generic SPI (GSPI) Controllers
Touch Host Controller (THC)
Intel® Serial I/O Universal Asynchronous Receiver/Transmitter (UART) Controllers
Private Configuration Space Port ID
Testability and Monitoring
Miscellaneous Signals
Security Technologies
Intel® Converged Boot Guard and Intel® TXT
Crypto Acceleration Instructions
Intel® Secure Key
Execute Disable Bit
Intel® Supervisor Mode Execution Protection (Intel® SMEP)
Intel® Supervisor Mode Access Protection (Intel® SMAP)
User Mode Instruction Prevention (UMIP)
Intel® System Resources Defense and Intel® System Security Report
Intel® Total Memory Encryption - Multi-Key
Control-flow Enforcement Technology (Intel® CET)
BIOS Guard
Intel® Platform Trust Technology
Linear Address Space Separation (LASS)
Security Firmware Engines
Audio Voice and Speech
Intel® High Definition Audio (Intel® HD Audio) Controller Capabilities
Audio DSP Capabilities
Intel® High Definition Audio Interface Capabilities
Direct Attached Digital Microphone (PDM) Interface
USB Audio Offload Support
Intel® Display Audio Interface
MIPI® SoundWire* Interface
Signal Description
Integrated Pull-Ups and Pull-Downs
I/O Signal Planes and States
Power Management
System Power States, Advanced Configuration and Power Interface (ACPI)
Legacy Power Management Support
Functional Description
Processor Power and Efficient P/LP E Cores Power Management
Processor Graphics Power Management
TCSS Power State
Power and Performance Technologies
Deprecated Technology
Power and Internal Signals
Power and Performance Technologies
Intel® Thread Director
Intel® Smart Cache Technology
P-core and LP E-core Level 0, Level 1 and Level 2 Caches
Ring Interconnect
Intel® Hybrid Technology
Intel® Turbo Boost Max Technology 3.0
Intel® Turbo Boost Technology 2.0
Intel® Adaptive Boost Technology
Intel System Agent Enhanced SpeedStep® Technology
Enhanced Intel SpeedStep® Technology
Intel® Speed Shift Technology
Intel® 64 Architecture x2APIC
Intel® Advanced Vector Extensions 2 (Intel® AVX2)
Intel® Dynamic Tuning Technology (Intel® DTT)
User Mode Wait Instructions
Cache Line Write Back (CLWB)
Thermal Management Features
Skin Temperature Control (STC)
Adaptive Thermal Monitor
Digital Thermal Sensor
PROCHOT# Signal
PROCHOT Demotion Algorithm
Voltage Regulator Protection using PROCHOT#
Thermal Solution Design and PROCHOT# Behavior
Low-Power States and PROCHOT# Behavior
THERMTRIP# Signal
Critical Temperature Detection
Low-Power Idle States
When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, deeper C-states have longer exit and entry latencies. Resolution of C-states occurs at the thread, processor P/LP E core, and processor package level. Thread-level C-States are available if the processor P/LP E core support multiple threads.
Idle Power Management Breakdown of the Processor P/LP E Cores
While individual threads can request low-power C-states, power saving actions only take place once the processor P/LP E core C-state is resolved. processor P/LP E core C-states are automatically resolved by the processor. For thread and processor P/LP E core C-states, a transition to and from C0 state is required before entering any other C-state.