Command Capabilities (CMDCAP) – Offset b0 - 001 - ID:872351 | Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers

Introduction
D0:F0 Host Bridge and DRAM Controller - GTTMMADR
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
- VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
- CAPID0_F PCI (CAPID0_F_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
- Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR)
- PM CONFIG THERM STATUS 0 0 0 MCHBAR (PM_CONFIG_THERM_STATUS_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit

Command Capabilities (CMDCAP) – Offset b0

The Command Capabilities register indicates which administrative commands are supported by the Command register. This register is a bitmask where each bit corresponds to the command with the same command code as the bit position. For example, bit 1 of this register corresponds to the Enable Device command (command code 1).

Bit Range	Default	Access	Field Name and Description
63:32	0h	RO/V	Upper 32 bits (UPPER) Each bit corresponds to a command code, and indicates whether that administrative command is supported. If the bit is 1, the corresponding command is supported; if the bit is 0, the corresponding command is not supported. Bits corresponding to undefined command codes are unused and are read as 0. Refer to #341204 for more details
31:0	1ffeh	RO/V	Lower 32 bits (LOWER) Each bit corresponds to a command code, and indicates whether that administrative command is supported. If the bit is 1, the corresponding command is supported; if the bit is 0, the corresponding command is not supported. Bits corresponding to undefined command codes are unused and are read as 0. Refer to #341204 for more details

Bit Range

Default

Access

Field Name and Description

63:32

RO/V

Upper 32 bits (UPPER)

Each bit corresponds to a command code, and indicates whether that
administrative command is supported. If the bit is 1, the corresponding
command is supported; if the bit is 0, the corresponding command is not
supported. Bits corresponding to undefined command codes are unused
and are read as 0.
Refer to #341204 for more details

31:0

1ffeh

RO/V

Lower 32 bits (LOWER)

Software Error (QW0) (SWERROR0)

Command Status (CMDSTATUS) Software Error (QW0) (SWERROR0)