15:6

0h

RO

Reserved

5

0h

RO/V

Transactions Pending (TP)

When Set, this bit indicates that the Function has issued Non-Posted Requests that have not been completed. This bit is cleared only when al outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism. This bit will also be cleared upon the completion of an FLR.

4

0h

RO

Reserved

3

0h

RW/1C/V

Unsupported Request Detected (URD)

This bit indicates that the Function received an Unsupported Request. Errors are logged in this register regardless of whether or not error reporting is enabled in the Device Control register.

2

0h

RW/1C/V

Fatal Error Detected (FED)

This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the Device Control register. Errors are logged in this register regardless of the settings of the AER Uncorrectable Error Mask register.

1

0h

RW/1C/V

Non-fatal Error Detected (NED)

This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the Device Control register. Errors are logged in this register regardless of the settings of the AER Uncorrectable Error Mask register.

0

0h

RW/1C/V

Correctable Error Detected (CED)

This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether or not error reporting is enabled in the Device Control register. Errors are logged in this register regardless of the settings of the AER Correctable Error Mask register.