MSI-X Permissions Table (MSIXPERM8) – Offset 240 - 001 - ID:872351 | Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers

Introduction
D0:F0 Host Bridge and DRAM Controller - GTTMMADR
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
- VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
- CAPID0_F PCI (CAPID0_F_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
- Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR)
- PM CONFIG THERM STATUS 0 0 0 MCHBAR (PM_CONFIG_THERM_STATUS_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit

MSI-X Permissions Table (MSIXPERM8) – Offset 240

The MSI-X Permissions Table is a set of 4-byte registers in BAR0 with the same number of entries as the MSI-X Table. The offset of the MSI-X Permissions Table is given by the MSI-X Permissions Offset field in the Table Offsets register. The number of entries is given by the PCIe-defined MSI-X capability. The individual registers in the table are on 8-byte boundaries.
Each register in the MSI-X Permissions Table corresponds to an entry in the MSI-X table and contains controls associated with that interrupt table entry. These controls are the same as those in the IMS, but these fields cannot be added to the MSI-X table itself, because it is defined by PCI-SIG.

Bit Range	Default	Access	Field Name and Description
31:12	0h	RW	MSIXPERM PASID (PASID) If PASID Enable is 1, this field is checked against the PASID field of the descriptor. See #341204 section 5.4.
11:4	0h	RO	Reserved
3	0h	RW	PASID Enable (PASIDEN) This field is checked against the WQ PASID Enable field of the WQ the descriptor was submitted to. See #341204 section 5.4.
2	0h	RW	MSIXPERM Ignore (IGNORE) If this field is 1 when a descriptor completion interrupt references the corresponding MSI-X table entry, no interrupt is generated and the Pending field is not set.This field does not prevent delivery of an interrupt if Pending is 1 and Mask is cleared.This field does not affect delivery of interrupts due to causes other than descriptor completion.
1:0	0h	RO	Reserved

Group Work Queue Configuration (GRPWQCFG0)

MSI-X Permissions Table (MSIXPERM7) Group Work Queue Configuration (GRPWQCFG0)