IBECC ECC Error Injection Control (ECC_INJ_CONTROL) – Offset d598 - 001 - ID:872351 | Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers

Introduction
D0:F0 Host Bridge and DRAM Controller - GTTMMADR
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
- VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
- CAPID0_F PCI (CAPID0_F_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
- Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR)
- PM CONFIG THERM STATUS 0 0 0 MCHBAR (PM_CONFIG_THERM_STATUS_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit

IBECC ECC Error Injection Control (ECC_INJ_CONTROL) – Offset d598

The ECC_INJ_CONTROL register configures the error injection mechanisms through the ECC _Inject field.

Bit Range	Default	Access	Field Name and Description
31:16	0h	RO	Reserved
15:8	0h	RW	Injection Count (COUNT) When ECC_INJECT mode is set to 0x3 or 0x7, inject an ECC error every time this counter expires. The ECC_Inject_count is incremented every time that a cache line is issued by IBECC in 64B ECC granularity mode. Else in 32B ECC granularity mode, the count increments every 32B issued by IBECC
7:3	0h	RO	Reserved
2:0	0h	RW	ECC Error Injection Mode (ECC_INJECT) Configures the error injection mechanism. 000b: No ECC error injection 001b: Inject a correctable ECC error on the ECC_INJ_ADDR_COMPARE register match 011b: Inject a correctable ECC error on the ECC error insertion counter 101b: Inject a non-recoverable ECC error on the ECC_INJ_ADDR_COMPARE register match 111b: Inject a non-recoverable ECC error on the ECC error insertion counter

Parity Error Injection (PARITY_ERR_INJ) Request Counter (ECC_VC0_SYND_RD_REQCOUNT)