Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 872351 | 04/14/2026 | 001 | Public |
IAA Capabilities (IAACAP) – Offset 180
IAA Capabilities
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 63:12 | 0h | RO | Reserved |
| 11 | 1h | RO/V | Crypto XTS Support (CRYPTOXTSSUPP) 0: Encryption and Decryption are not supported with the XTS algorithm. |
| 10 | 1h | RO/V | Crypto CFB Support (CRYPTOCFBSUPP) 0: Encryption and Decryption are not supported with the CFB algorithm |
| 9 | 1h | RO/V | Crypto GCM Support (CRYPTOGCMSUPP) 0: Encryption and Decryption are not supported with the GCM algorithm |
| 8 | 1h | RO/V | Header Generation Support (HEADERGENSUPP) 0: Compression Header Generation is not supported. |
| 7 | 1h | RO/V | Dictionary Compression Support (DICTIONARYCMPSUPP) 0: Compression with a dictionary is not supported. |
| 6 | 0h | RO | Reserved |
| 5 | 1h | RO/V | Compression Early Abort Support (CMPEARLYABORTSUPP) 0: Compression Early Abort is not supported. |
| 4 | 1h | RO/V | Load Partial AECS Support (LOADPARTIALAECSSUPP) 0: If the Decompress Flag bit 13 (Load Partial) is set, then the descriptor will return an error. |
| 3 | 1h | RO/V | Force Array Output Modification Support (FORCEARRAYOUTPUTMODSUPP) 0: If the Filter Flag bit 27 (Force Array Output Modification) is set, then the descriptor will return an error. |
| 2 | 1h | RO/V | Chaining to CRC64/Zero Compress Functions (CHAININGCRC64ZCMPFUNC) 0: Operation CRC64 cannot be preceded by any other operation. |
| 1 | 1h | RO/V | Drop Initial Bits Support (DROPINITIALBITSSUPP) 0: If the Drop Initial Bits field in the AECS is non-zero, the descriptor will return an error. |
| 0 | 1h | RO/V | Generation 2 Minimum Capabilities (DCMPAECSFORMATVER) 0: Minimum Generation 2 features are not present, in particular: |