Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 872351 | 04/14/2026 | 001 | Public |
WQ Configuration E (WQCFGE3) – Offset 4d0
WQ Configuration E
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:17 | 0h | RO | Reserved |
| 16 | 0h | RW/L | WQ Occupancy Interrupt Table (OIT) 0: WQ Occupancy Interrupt Handle is a handle for the MSI-X table. |
| 15:0 | 0h | RW/L | WQ Occupancy Interrupt Handle (OIH) An interrupt handle indicating which interrupt table entry to use to generate the interrupt. |