Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 872351 | 04/14/2026 | 001 | Public |
Device Control (DEVCTL) – Offset 48
Controls PCI Express device specific parameters
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 15 | 0h | RW/V | Initiate Function Level Reset (IFLR) A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b. |
| 14:12 | 2h | RW | Max Read Request Size (MRRS) This field sets the maximum Read Request size for the Function as a Requester. |
| 11 | 1h | RW | Enable No Snoop (ENS) If this bit is Set, the Function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency. |
| 10:9 | 0h | RO | Reserved |
| 8 | 1h | RW | Extended Tag Field Enable (ETFE) This bit, in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register, determines how many Tag field bits a Requester is permitted to use. |
| 7:5 | 0h | RW | Max Payload Size (MPS) This field sets the maximum TLP payload size for the Function. |
| 4 | 1h | RW | Enable Relaxed Ordering (ERO) If this bit is Set, the Function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering. |
| 3 | 0h | RW | Unsupported Request Reporting Enable (URRE) This bit, in conjunction with other bits, controls the signaling of unsupported Request Errors by sending error Messages. |
| 2 | 0h | RW | Fatal Error Reporting Enable (FERE) This bit, in conjunction with other bits, controls sending ERR_FATAL Messages. |
| 1 | 0h | RW | Non-Fatal Error Reporting Enable (NERE) This bit, in conjunction with other bits, controls sending ERR_NONFATAL Messages. |
| 0 | 0h | RW | Correctable Error Reporting Enable (CERE) This bit, in conjunction with other bits, controls sending ERR_COR Messages. |