Parity Error Log (PARITY_ERR_LOG) – Offset d578 - 001 - ID:872351 | Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers

Introduction
D0:F0 Host Bridge and DRAM Controller - GTTMMADR
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
- VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
- CAPID0_F PCI (CAPID0_F_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
- Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR)
- PM CONFIG THERM STATUS 0 0 0 MCHBAR (PM_CONFIG_THERM_STATUS_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit

Parity Error Log (PARITY_ERR_LOG) – Offset d578

PARITY_ERR_LOG register is used to store the error status information in parity enabled configurations along with the CMI address information of the address block of main memory in which an error has occurred.

Bit Range	Default	Access	Field Name and Description
63	0h	RW/1C/V/P	Error Status (ERR_STS) Set by hardware, cleared by software when written to 1.
62:60	0h	RO/V/P	Error Type (ERR_TYPE) Indicates the type of parity error ( 0x0 Read request address , 0x1 = write request header, 0x2 = write request data, 0x3 = read completion header, 0x4 = read completion data)
59:39	0h	RO	Reserved
38:5	0h	RO/V/P	Error Address (ERR_ADDRESS) CMI address of the address block of main memory of which a parity error has occurred.
4	0h	RO/V/P	Parity Error Overflow (PERR_OVERFLOW) This bit is set when a parity error occurs and the PERRSTS bit is already set, indicating that more than one error has occurred. Hardware will clear it if PERRSTS is cleared by SB write
3:0	0h	RO	Reserved

ECC Injection Address Mask (ECC_INJ_ADDR_MASK)

ECC Error Log (ECC_ERROR_LOG) ECC Injection Address Mask (ECC_INJ_ADDR_MASK)