Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers

ID Date Version Classification
872351 04/14/2026 001 Public
Document Table of Contents
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5) In-Band ECC Activate (IBECC_ACTIVATE) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_0) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_1) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_2) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_3) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_4) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_5) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_6) IBECC Protected Address Range (IBECC_PROTECT_ADDR_RANGE_7) ECC Protected VC0 Read Data Request Count (ECC_VC0_RD_REQCOUNT) ECC Protected VC1 Read Data Request Count (ECC_VC1_RD_REQCOUNT) ECC Protected VC0 Write Data Request Count (ECC_VC0_WR_REQCOUNT) ECC Protected VC1 Write Data Request Count (ECC_VC1_WR_REQCOUNT) Unprotected VC0 Read Request Count (NOECC_VC0_RD_REQCOUNT) Unprotected VC1 Read Request Count (NOECC_VC1_RD_REQCOUNT) Unprotected VC0 Write Request Count (NOECC_VC0_WR_REQCOUNT) Unprotected VC1 Write Request Count (NOECC_VC1_WR_REQCOUNT) ECC Error Log (ECC_ERROR_LOG) Parity Error Log (PARITY_ERR_LOG) ECC Injection Address Mask (ECC_INJ_ADDR_MASK) ECC Error Injection Address Base (ECC_INJ_ADDR_BASE) Parity Error Injection (PARITY_ERR_INJ) IBECC ECC Error Injection Control (ECC_INJ_CONTROL) Request Counter (ECC_VC0_SYND_RD_REQCOUNT) Request Counter (ECC_VC1_SYND_RD_REQCOUNT) Request Counter (ECC_VC0_SYND_WR_REQCOUNT) Request Counter (ECC_VC1_SYND_WR_REQCOUNT) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_0) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_1) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_2) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_3) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_4) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_5) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_6) ECC Data Storage Address (ECC_STORAGE_ADDR_RANGE_7) ECC Error Counter (ECC_ERR_COUNT) IBECC Memory Initialization Control (IBECC_MEMORY_INIT_CONTROL) Hashing Control (IBECC_ADDR_HASH)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management (BIOS_POST_CODE_0_0_0_MCHBAR_PCU) Cycle Sum of All Active Cores (PKG_IA_C0_ANY_SUM_0_0_0_MCHBAR_PCU) Cycle Sum of Any Active Core (PKG_IA_C0_ANY_0_0_0_MCHBAR_PCU) (PKG_IA_C0_ANY_RATIO_0_0_0_MCHBAR_PCU) (PACKAGE_RAPL_PERF_STATUS_0_0_0_MCHBAR_PCU) SA_PERF_STATUS0 (SA_PERF_STATUS0_0_0_0_MCHBAR_PCU) (PRIP_NRG_STTS_0_0_0_MCHBAR_PCU) (SECP_NRG_STTS_0_0_0_MCHBAR_PCU) Package power sku unit (PACKAGE_POWER_SKU_UNIT_0_0_0_MCHBAR_PCU) Package energy status (PACKAGE_ENERGY_STATUS_0_0_0_MCHBAR_PCU) sa perf status1 (SA_PERF_STATUS1_0_0_0_MCHBAR_PCU) Power Plane 0 Efficient Cycles (PP0_EFFICIENT_CYCLES_0_0_0_MCHBAR_PCU) (PP0_TEMPERATURE_0_0_0_MCHBAR_PCU) (RP_STATE_LIMITS_0_0_0_MCHBAR_PCU) GT PState CAP (GT_PSTATE_CAP_0_0_0_MCHBAR_PCU) Temperature Target (TEMPERATURE_TARGET_0_0_0_MCHBAR_PCU) (PACKAGE_RAPL_LIMIT_0_0_0_MCHBAR_PCU) Thermal Status GT (THERM_STATUS_GT_0_0_0_MCHBAR_PCU) Thermal Interrupt GT (therm_interrupt_GT_0_0_0_MCHBAR_PCU) (DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU) DLVR RFI/EMI Control Register (RFI_EMI_CONTROL_0_0_0_MCHBAR_PCU) (CORE_PERF_MIN_MAX_0_0_0_MCHBAR) (PLATFORM_TEMPERATURE_CONTROL_SENSOR_0_0_0_0_MCHBAR) (PLATFORM_TEMPERATURE_CONTROL_SENSOR_1_0_0_0_MCHBAR) (PLATFORM_TEMPERATURE_CONTROL_SENSOR_2_0_0_0_MCHBAR) (BIOS_Mailbox_Data_0_0_0_MCHBAR_PCU) (BIOS_Mailbox_Interface_0_0_0_MCHBAR_PCU) (BIOS_RESET_CPL_0_0_0_MCHBAR_PCU) ISYS Control (ISYS_CONTROL_0_0_0_MCHBAR) (CONFIG_TDP_NOMINAL_0_0_0_MCHBAR_PCU) (CONFIG_TDP_LEVEL1_0_0_0_MCHBAR_PCU) (CONFIG_TDP_LEVEL2_0_0_0_MCHBAR_PCU) (CONFIG_TDP_CONTROL_0_0_0_MCHBAR_PCU) (TURBO_ACTIVATION_RATIO_0_0_0_MCHBAR_PCU) (OC_STATUS_0_0_0_MCHBAR_PCU) (BCLK_FREQ_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR Version Register (VER_REG_0_0_0_VTDBAR) Capability Register (CAP_REG_0_0_0_VTDBAR) Extended Capability Register (ECAP_REG_0_0_0_VTDBAR) Global Command Register (GCMD_REG_0_0_0_VTDBAR) General Status Register (GSTS_REG_0_0_0_VTDBAR) Root Table Address Register (RTADDR_REG_0_0_0_VTDBAR) Context Command Register (CCMD_REG_0_0_0_VTDBAR) Fault Status Register (FSTS_REG_0_0_0_VTDBAR) Fault Event Control Register (FECTL_REG_0_0_0_VTDBAR) Fault Event Data Register (FEDATA_REG_0_0_0_VTDBAR) Fault Event Address Register (FEADDR_REG_0_0_0_VTDBAR) Fault Event Upper Address Register (FEUADDR_REG_0_0_0_VTDBAR) Advanced Fault Log Register (AFLOG_REG_0_0_0_VTDBAR) Protected Memory Enable Register (PMEN_REG_0_0_0_VTDBAR) Protected Low Memory Base Register (PLMBASE_REG_0_0_0_VTDBAR) Protected Low-Memory Limit Register (PLMLIMIT_REG_0_0_0_VTDBAR) Protected High-Memory Base Register (PHMBASE_REG_0_0_0_VTDBAR) Protected High-Memory Limit Register (PHMLIMIT_REG_0_0_0_VTDBAR) Invalidation Queue Head Register (IQH_REG_0_0_0_VTDBAR) Invalidation Queue Tail Register (IQT_REG_0_0_0_VTDBAR) Invalidation Queue Address Register (IQA_REG_0_0_0_VTDBAR) Invalidation Completion Status Register (ICS_REG_0_0_0_VTDBAR) Invalidation Event Control Register (IECTL_REG_0_0_0_VTDBAR) Invalidation Event Data Register (IEDATA_REG_0_0_0_VTDBAR) Invalidation Event Address Register (IEADDR_REG_0_0_0_VTDBAR) Invalidation Event Upper Address Register (IEUADDR_REG_0_0_0_VTDBAR) IQ Error Info register (IQERCD_REG_0_0_0_VTDBAR) Interrupt Remapping Table Address Register (IRTA_REG_0_0_0_VTDBAR) Page Request Queue Head Register (PQH_REG_0_0_0_VTDBAR) Page Request Queue Tail Register (PQT_REG_0_0_0_VTDBAR) Page Request Queue Address Register (PQA_REG_0_0_0_VTDBAR) Page Request Status Register (PRS_REG_0_0_0_VTDBAR) Page Request Event Control Register (PECTL_REG_0_0_0_VTDBAR) Page Request Event Data Register (PEDATA_REG_0_0_0_VTDBAR) Page Request Event Address Register (PEADDR_REG_0_0_0_VTDBAR) Page Request Event Upper Address Register (PEUADDR_REG_0_0_0_VTDBAR) MTRR Capability Register (MTRRCAP_0_0_0_VTDBAR) MTRR Default Type Register (MTRRDEFAULT_0_0_0_VTDBAR) Fixed-Range MTRR Format 64K-00000 (MTRR_FIX64K_00000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-80000 (MTRR_FIX16K_80000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 16K-A0000 (MTRR_FIX16K_A0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C0000 (MTRR_FIX4K_C0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-C8000 (MTRR_FIX4K_C8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D0000 (MTRR_FIX4K_D0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-D8000 (MTRR_FIX4K_D8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E0000 (MTRR_FIX4K_E0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-E8000 (MTRR_FIX4K_E8000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F0000 (MTRR_FIX4K_F0000_REG_0_0_0_VTDBAR) Fixed-Range MTRR Format 4K-F8000 (MTRR_FIX4K_F8000_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 0 (MTRR_PHYSBASE0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 0 (MTRR_PHYSMASK0_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 1 (MTRR_PHYSBASE1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 1 (MTRR_PHYSMASK1_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 2 (MTRR_PHYSBASE2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 2 (MTRR_PHYSMASK2_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 3 (MTRR_PHYSBASE3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 3 (MTRR_PHYSMASK3_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 4 (MTRR_PHYSBASE4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 4 (MTRR_PHYSMASK4_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 5 (MTRR_PHYSBASE5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 5 (MTRR_PHYSMASK5_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 6 (MTRR_PHYSBASE6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 6 (MTRR_PHYSMASK6_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 7 (MTRR_PHYSBASE7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 7 (MTRR_PHYSMASK7_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 8 (MTRR_PHYSBASE8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 8 (MTRR_PHYSMASK8_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Base 9 (MTRR_PHYSBASE9_REG_0_0_0_VTDBAR) Variable-Range MTRR Format Physical Mask 9 (MTRR_PHYSMASK9_REG_0_0_0_VTDBAR) Performance Monitoring Capabilities (PERFCAP_0_0_0_VTDBAR) Performance Monitoring Configuration Offset (PERFCFGOFF_0_0_0_VTDBAR) Performance Monitoring Freeze Offset (PERFFRZOFF_0_0_0_VTDBAR) Performance Monitoring Overflow Offset (PERFOVFOFF_0_0_0_VTDBAR) Performance Monitoring Counter Offset (PERFCNTOFF_0_0_0_VTDBAR) Performance Interrupt Status (PERFINTRSTS_0_0_0_VTDBAR) Performance Interrupt Control (PERFINTRCTL_0_0_0_VTDBAR) Performance Interrupt Data (PERFINTRDATA_0_0_0_VTDBAR) Performance Interrupt Address (PERFINTRADDR_0_0_0_VTDBAR) Performance Interrupt Upper Address (PERFINTRUADDR_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP0_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP1_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP2_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP3_0_0_0_VTDBAR) Performance Monitoring Event Capabilities (PERFEVNTCAP4_0_0_0_VTDBAR) Enhanced Command (ECMD_0_0_0_VTDBAR) Enhanced Command Response (ERESP_0_0_0_VTDBAR) Enhanced Command Capabilities (ECMD_CAP3_0_0_0_VTDBAR) Fault Recording Register Low [0] (FRCDL_REG_0_0_0_VTDBAR) Fault Recording Register High [0] (FRCDH_REG_0_0_0_VTDBAR) Invalidate Address Register (IVA_REG_0_0_0_VTDBAR) IOTLB Invalidate Register (IOTLB_REG_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR0_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP0_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR1_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP1_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR2_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP2_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR3_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP3_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG4_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR4_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP4_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG5_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR5_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP5_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG6_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR6_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP6_0_0_0_VTDBAR) Performance Monitoring Counter Configuration (PERFCNTRCFG7_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR0_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR1_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR2_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR3_0_0_0_VTDBAR) Performance Monitoring Filter Configuration (PERFCNTR7_FLTR4_0_0_0_VTDBAR) Performance Monitoring Counter Capabilities (PERFCNTRCAP7_0_0_0_VTDBAR) Performance Monitoring Counter Event Capabilities (PERFCNTRCAP7_EG0_0_0_0_VTDBAR) Performance Monitoring Freeze (PERFFRZ0_0_0_0_VTDBAR) Performance Monitoring Overflow Status (PERFOVFSTS0_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR0_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR1_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR2_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR3_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR4_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR5_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR6_0_0_0_VTDBAR) Performance Monitoring Counter (PERFCNTR7_0_0_0_VTDBAR)
D11:F0 Vision Processing Unit Device ID and Vendor ID (DEVVENDID) Status and Command (STATUSCOMMAND) Revision ID and Class Code (REVCLASSCODE) Cache Line Latency Header and BIST (CLLATHEADERBIST) Base Address Register (BAR) Base Address Register High (BAR_HIGH) Base Address Register1 (BAR1) Base Address Register1 High (BAR1_HIGH) Base Address Register (BAR2) Base Address Register High (BAR2_HIGH) Subsystem Vendor and Subsystem ID (SUBSYSTEMID) Expansion ROM Base Address (EXPANSION_ROM_BASEADDR) Capabilities Pointer (CAPABILITYPTR) Interrupt (INTERRUPTREG) PCIe Capabilities (PCIECAPREG) PCIe Device Capability (DEVCAPREG) PCIe Device Control Status (DEVCTRLSTAT) PCIe Device Capability2 (DEVCAPREG2) PCIe Device Control2 Status (DEVCTRLSTAT2) Power Management Capability ID (POWERCAPID) Power Management Control And Status (PMECTRLSTATUS) PCI Device Idle Vendor Capability (PCIDEVIDLE_CAP_RECORD) Vendor Specific Extended Capability (DEVID_VEND_SPECIFIC_REG) Software LTR Update MMIO Location (D0I3_CONTROL_SW_LTR_MMIO_REG) Device Idle Pointer (DEVICE_IDLE_POINTER_REG) D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG) General Purpose Input (GEN_INPUT_REG) MSI Capability (MSI_CAP_REG) MSI Message Low Address (MSI_ADDR_LOW) MSI Message High Address (MSI_ADDR_HIGH) MSI Message Data (MSI_MSG_DATA) MSI Mask (MSI_MASK) MSI Pending (MSI_PENDING) Manufacturers ID (MANID) ATS Extended Capability Header (ATS_EXT_CAP_HEAD) ATS Capability and Control (ATS_CAP_CONTROL_HEAD) PASID Capability Header (PASID_CAP_HEAD) PASID Capability and Control (PASID_CAP_CONTROL_REG) PRS Capability Header (PRS_CAP_HEAD) PRS Control and Status (PRS_CONTROL_STATUS_REG) PRS Page Request Capacity (PRS_PAGE_REQ_CAPACITY) PRS Page Request Allocation (PRS_PAGE_REQ_ALLOC) SIOV Capability Header 1 (SIOV_CAP_HEAD_1) SIOV Capability Header 2 (SIOV_CAP_HEAD_2) SIOV Capability Header 3 (SIOV_CAP_HEAD_3) SIOV Support Page Size (SIOV_SUPP_PAGE_SZ) SIOV System Page Size (SIOV_SYSTEM_PAGE_SZ) SIOV Internal Capabilities (SIOV_INTERNAL_CAPABILITIES)
D12:F0 Intel© In-Memory Analytic Accelerator Config Space Vendor ID (VID) Device ID (DID) PCI Command (PCICMD) PCI Status (PCISTS) Revision ID (RID) Class Code Register-Level Programming Interface (CCRLPI) Class Code Sub-Class (CCSC) Class Code Base Class (CCBC) Cache Line Size (CLS) Latency Timer (LATTMR) Header Type (HDR) Built-in Self-Test (BIST) Base Address 0 (BAR0) Base Address 2 (BAR2) Sub-System Vendor ID (SSVID) Sub-System ID (SSID) Capabilities Pointer (CAPPTR) Interrupt Line (INTL) Interrupt Pin (INTP) Minimum Grant (MINGNT) Maximum Latency (MAXLAT) PCI Express Capability List (PCIECAPLST) PCI Express Capabilities (PCIECAP) Device Capabilities (DEVCAP) Device Control (DEVCTL) Device Status (DEVSTS) Device Capabilities 2 (DEVCAP2) Device Control 2 (DEVCTL2) MSI-X Capability Header (MSIXCAPLST) MSI-X Message Control (MSIXMSGCTL) MSI-X Table (MSIXTBL) MSI-X Pending Bit Array (MSIXPBA) Power Management Capabilities (PMCAP) Power Management Control/Status (PMCSR) ATS Extended Capability Header (ATSEXTCAP) ATS Capability (ATSCAP) ATS Control (ATSCTL) Scalable IOV Extended Capability Header (SIOVEXTCAP) Scalable IOV Designated Vendor-Specific Header 1 (SIOVDVSEC1) Scalable IOV Designated Vendor-Specific Header 2 (SIOVDVSEC2) Scalable IOV Function Dependency Link (SIOVFDL) Scalable IOV Flags (SIOVFLAGS) SIOV Supported Page Sizes (SIOVSUPPGSZ) SIOV System Page Size (SIOVSYSPGSZ) SIOV Capabilities (SIOVCAP) PASID Extended Capability Header (PASIDEXTCAP) PASID Capability (PASIDCAP) PASID Control (PASIDCTL) Page Request Extended Capability Header (PRSEXTCAP) Page Request Control (PRSCTL) Page Request Status (PRSSTS) Outstanding Page Request Capacity (PRSREQCAP) Outstanding Page Request Allocation (PRSREQALLOC) AER Extended Capability Header (AEREXTCAP) Uncorrectable Error Status (ERRUNCSTS) Uncorrectable Error Mask (ERRUNCMSK) Uncorrectable Error Severity (ERRUNCSEV) Correctable Error Status (ERRCORSTS) Correctable Error Mask (ERRCORMSK) AER Capabilities and Control (AERCAPCTL) Header Log DW1 (AERHDRLOG1) Header Log DW2 (AERHDRLOG2) Header Log DW3 (AERHDRLOG3) Header Log DW4 (AERHDRLOG4) TLP Prefix Log Register DW1 (AERTLPPLOG1) TLP Prefix Log Register DW2 (AERTLPPLOG2) TLP Prefix Log Register DW3 (AERTLPPLOG3) TLP Prefix Log Register DW4 (AERTLPPLOG4)
D12:F0 Intel© In-Memory Analytic Accelerator Memory Space IAA Version (VERSION) General Capabilities (GENCAP) Work Queue Capabilities (WQCAP) Group Capabilities (GRPCAP) Engine Capabilities (ENGCAP) Operations Capability 0 (OPCAP0) Operations Capability 1 (OPCAP1) Operations Capability 2 (OPCAP2) Operations Capability 3 (OPCAP3) Table Offsets 0 (OFFSETS0) Table Offsets 1 (OFFSETS1) General Configuration (GENCFG) General Control (GENCTRL) General Status (GENSTS) Interrupt Cause (INTCAUSE) Command (CMD) Command Status (CMDSTATUS) Command Capabilities (CMDCAP) Software Error (QW0) (SWERROR0) Software Error (QW1) (SWERROR1) Software Error (QW2) (SWERROR2) Event Log Configuration 0 (EVLCFG0) Event Log Configuration 1 (EVLCFG1) Event Log Status (EVLSTATUS) IAA Capabilities (IAACAP) MSI-X Permissions Table (MSIXPERM0) MSI-X Permissions Table (MSIXPERM1) MSI-X Permissions Table (MSIXPERM2) MSI-X Permissions Table (MSIXPERM3) MSI-X Permissions Table (MSIXPERM4) MSI-X Permissions Table (MSIXPERM5) MSI-X Permissions Table (MSIXPERM6) MSI-X Permissions Table (MSIXPERM7) MSI-X Permissions Table (MSIXPERM8) Group Work Queue Configuration (GRPWQCFG0) Group Engine Configuration (GRPENGCFG0) Group Flags (GRPFLAGS0) Group Work Queue Configuration (GRPWQCFG1) Group Engine Configuration (GRPENGCFG1) Group Flags (GRPFLAGS1) Group Work Queue Configuration (GRPWQCFG2) Group Engine Configuration (GRPENGCFG2) Group Flags (GRPFLAGS2) Group Work Queue Configuration (GRPWQCFG3) Group Engine Configuration (GRPENGCFG3) Group Flags (GRPFLAGS3) WQ Configuration A (WQCFGA0) WQ Configuration B (WQCFGB0) WQ Configuration C (WQCFGC0) WQ Configuration D (WQCFGD0) WQ Configuration E (WQCFGE0) WQ Configuration F (WQCFGF0) WQ Configuration G (WQCFGG0) WQ Operations Capability A (WQOPCFGA0) WQ Operations Capability B (WQOPCFGB0) WQOperations Capability C (WQOPCFGC0) WQ Operations Capability D (WQOPCFGD0) WQ Configuration A (WQCFGA1) WQ Configuration B (WQCFGB1) WQ Configuration C (WQCFGC1) WQ Configuration D (WQCFGD1) WQ Configuration E (WQCFGE1) WQ Configuration F (WQCFGF1) WQ Configuration G (WQCFGG1) WQ Operations Capability A (WQOPCFGA1) WQ Operations Capability B (WQOPCFGB1) WQOperations Capability C (WQOPCFGC1) WQ Operations Capability D (WQOPCFGD1) WQ Configuration A (WQCFGA2) WQ Configuration B (WQCFGB2) WQ Configuration C (WQCFGC2) WQ Configuration D (WQCFGD2) WQ Configuration E (WQCFGE2) WQ Configuration F (WQCFGF2) WQ Configuration G (WQCFGG2) WQ Operations Capability A (WQOPCFGA2) WQ Operations Capability B (WQOPCFGB2) WQOperations Capability C (WQOPCFGC2) WQ Operations Capability D (WQOPCFGD2) WQ Configuration A (WQCFGA3) WQ Configuration B (WQCFGB3) WQ Configuration C (WQCFGC3) WQ Configuration D (WQCFGD3) WQ Configuration E (WQCFGE3) WQ Configuration F (WQCFGF3) WQ Configuration G (WQCFGG3) WQ Operations Capability A (WQOPCFGA3) WQ Operations Capability B (WQOPCFGB3) WQOperations Capability C (WQOPCFGC3) WQ Operations Capability D (WQOPCFGD3) WQ Configuration A (WQCFGA4) WQ Configuration B (WQCFGB4) WQ Configuration C (WQCFGC4) WQ Configuration D (WQCFGD4) WQ Configuration E (WQCFGE4) WQ Configuration F (WQCFGF4) WQ Configuration G (WQCFGG4) WQ Operations Capability A (WQOPCFGA4) WQ Operations Capability B (WQOPCFGB4) WQOperations Capability C (WQOPCFGC4) WQ Operations Capability D (WQOPCFGD4) WQ Configuration A (WQCFGA5) WQ Configuration B (WQCFGB5) WQ Configuration C (WQCFGC5) WQ Configuration D (WQCFGD5) WQ Configuration E (WQCFGE5) WQ Configuration F (WQCFGF5) WQ Configuration G (WQCFGG5) WQ Operations Capability A (WQOPCFGA5) WQ Operations Capability B (WQOPCFGB5) WQOperations Capability C (WQOPCFGC5) WQ Operations Capability D (WQOPCFGD5) WQ Configuration A (WQCFGA6) WQ Configuration B (WQCFGB6) WQ Configuration C (WQCFGC6) WQ Configuration D (WQCFGD6) WQ Configuration E (WQCFGE6) WQ Configuration F (WQCFGF6) WQ Configuration G (WQCFGG6) WQ Operations Capability A (WQOPCFGA6) WQ Operations Capability B (WQOPCFGB6) WQOperations Capability C (WQOPCFGC6) WQ Operations Capability D (WQOPCFGD6) WQ Configuration A (WQCFGA7) WQ Configuration B (WQCFGB7) WQ Configuration C (WQCFGC7) WQ Configuration D (WQCFGD7) WQ Configuration E (WQCFGE7) WQ Configuration F (WQCFGF7) WQ Configuration G (WQCFGG7) WQ Operations Capability A (WQOPCFGA7) WQ Operations Capability B (WQOPCFGB7) WQOperations Capability C (WQOPCFGC7) WQ Operations Capability D (WQOPCFGD7) Performance Monitoring Capabilities (PERFCAP) Performance Monitoring Reset Control (PERFRST) Peformance Monitoring Freeze (PRFFRZ) Performance Monitoring Overflow Status (OVFSTATUS) Performance Monitoring Event Capabilities (EVNTCAP_0) Performance Monitoring Event Capabilities (EVNTCAP_1) Performance Monitoring Event Capabilities (EVNTCAP_2) Performance Monitoring Event Capabilities (EVNTCAP_3) Performance Monitoring Event Capabilities (EVNTCAP_4) Performance Monitoring Event Capabilities (EVNTCAP_5) Counter Configuration (CNTRCFG_0) Counter Configuration (CNTRCFG_1) Counter Configuration (CNTRCFG_2) Counter Configuration (CNTRCFG_3) Counter Configuration (CNTRCFG_4) Counter Configuration (CNTRCFG_5) Counter Configuration (CNTRCFG_6) Counter Configuration (CNTRCFG_7) Counter Data (CNTRDATA_0) Counter Data (CNTRDATA_1) Counter Data (CNTRDATA_2) Counter Data (CNTRDATA_3) Counter Data (CNTRDATA_4) Counter Data (CNTRDATA_5) Counter Data (CNTRDATA_6) Counter Data (CNTRDATA_7) Filter Configuration - WQ (FILTCFG_WQ_0) Filter Configuration - Traffic Class (TC) (FILTCFG_TC_0) Filter Configuration - Page Size (FILTCFG_PGSZ_0) Filter Configuration - Transfer Size (FILTCFG_SZ_0) Filter Configuration - Engine Number (FILTCFG_ENG_0) Filter Configuration - PASID (FILTCFG_PASID_0) Filter Configuration - WQ (FILTCFG_WQ_1) Filter Configuration - Traffic Class (TC) (FILTCFG_TC_1) Filter Configuration - Page Size (FILTCFG_PGSZ_1) Filter Configuration - Transfer Size (FILTCFG_SZ_1) Filter Configuration - Engine Number (FILTCFG_ENG_1) Filter Configuration - PASID (FILTCFG_PASID_1) Filter Configuration - WQ (FILTCFG_WQ_2) Filter Configuration - Traffic Class (TC) (FILTCFG_TC_2) Filter Configuration - Page Size (FILTCFG_PGSZ_2) Filter Configuration - Transfer Size (FILTCFG_SZ_2) Filter Configuration - Engine Number (FILTCFG_ENG_2) Filter Configuration - PASID (FILTCFG_PASID_2) Filter Configuration - WQ (FILTCFG_WQ_3) Filter Configuration - Traffic Class (TC) (FILTCFG_TC_3) Filter Configuration - Page Size (FILTCFG_PGSZ_3) Filter Configuration - Transfer Size (FILTCFG_SZ_3) Filter Configuration - Engine Number (FILTCFG_ENG_3) Filter Configuration - PASID (FILTCFG_PASID_3) Filter Configuration - WQ (FILTCFG_WQ_4) Filter Configuration - Traffic Class (TC) (FILTCFG_TC_4) Filter Configuration - Page Size (FILTCFG_PGSZ_4) Filter Configuration - Transfer Size (FILTCFG_SZ_4) Filter Configuration - Engine Number (FILTCFG_ENG_4) Filter Configuration - PASID (FILTCFG_PASID_4) Filter Configuration - WQ (FILTCFG_WQ_5) Filter Configuration - Traffic Class (TC) (FILTCFG_TC_5) Filter Configuration - Page Size (FILTCFG_PGSZ_5) Filter Configuration - Transfer Size (FILTCFG_SZ_5) Filter Configuration - Engine Number (FILTCFG_ENG_5) Filter Configuration - PASID (FILTCFG_PASID_5) Filter Configuration - WQ (FILTCFG_WQ_6) Filter Configuration - Traffic Class (TC) (FILTCFG_TC_6) Filter Configuration - Page Size (FILTCFG_PGSZ_6) Filter Configuration - Transfer Size (FILTCFG_SZ_6) Filter Configuration - Engine Number (FILTCFG_ENG_6) Filter Configuration - PASID (FILTCFG_PASID_6) Filter Configuration - WQ (FILTCFG_WQ_7) Filter Configuration - Traffic Class (TC) (FILTCFG_TC_7) Filter Configuration - Page Size (FILTCFG_PGSZ_7) Filter Configuration - Transfer Size (FILTCFG_SZ_7) Filter Configuration - Engine Number (FILTCFG_ENG_7) Filter Configuration - PASID (FILTCFG_PASID_7) MSI-X Message Address (MSIXADDR0) MSI-X Message Data (MSIXDATA0) MSI-X Vector Control (MSIXVECCTL0) MSI-X Message Address (MSIXADDR1) MSI-X Message Data (MSIXDATA1) MSI-X Vector Control (MSIXVECCTL1) MSI-X Message Address (MSIXADDR2) MSI-X Message Data (MSIXDATA2) MSI-X Vector Control (MSIXVECCTL2) MSI-X Message Address (MSIXADDR3) MSI-X Message Data (MSIXDATA3) MSI-X Vector Control (MSIXVECCTL3) MSI-X Message Address (MSIXADDR4) MSI-X Message Data (MSIXDATA4) MSI-X Vector Control (MSIXVECCTL4) MSI-X Message Address (MSIXADDR5) MSI-X Message Data (MSIXDATA5) MSI-X Vector Control (MSIXVECCTL5) MSI-X Message Address (MSIXADDR6) MSI-X Message Data (MSIXDATA6) MSI-X Vector Control (MSIXVECCTL6) MSI-X Message Address (MSIXADDR7) MSI-X Message Data (MSIXDATA7) MSI-X Vector Control (MSIXVECCTL7) MSI-X Message Address (MSIXADDR8) MSI-X Message Data (MSIXDATA8) MSI-X Vector Control (MSIXVECCTL8) MSI-X Pending Bit Array (MSIXPB)
D2:F0 Processor Graphics Vendor Identification (VID2_0_2_0_PCI) Device Identification (DID2_0_2_0_PCI) PCI Command (PCICMD_0_2_0_PCI) PCI Status (PCISTS2_0_2_0_PCI) Revision Identification and Class Code register (RID2_CC_0_2_0_PCI) Cache Line Size (CLS_0_2_0_PCI) Master Latency Timer (MLT2_0_2_0_PCI) Header Type (HDR2_0_2_0_PCI) Built In Self Test (BIST_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) Graphics Translation Table Memory Mapped Range Address (GTTMMADR1_0_2_0_PCI) Local Memory Bar (LMEMBAR0_0_2_0_PCI) Local Memory Bar (LMEMBAR1_0_2_0_PCI) Subsystem Vendor Identification (SVID2_0_2_0_PCI) Subsystem Identification (SID2_0_2_0_PCI) Video BIOS ROM Base Address (ROMADR_0_2_0_PCI) Capabilities Pointer (CAPPOINT_0_2_0_PCI) Interrupt Line (INTRLINE_0_2_0_PCI) Interrupt Pin (INTRPIN_0_2_0_PCI) Minimum Grant (MINGNT_0_2_0_PCI) Maximum Latency (MAXLAT_0_2_0_PCI) Capability Identifier (CAPID0_0_2_0_PCI) Capabilities Control (CAPCTRL0_0_2_0_PCI) Capabilities A (CAPID0_A_0_2_0_PCI) PCI Mirror of GMCH Graphics Control (MGGC0_0_2_0_PCI) PCI Express Capability Header (PCIECAPHDR_0_2_0_PCI) PCI Express Capability (PCIECAP_0_2_0_PCI) Device Capabilities (DEVICECAP_0_2_0_PCI) PCI Express Device Control (DEVICECTL_0_2_0_PCI) PCI Express Device Status Register (DEVICESTS_0_2_0_PCI) Link Capabilities (LINKCAP_0_2_0_PCI) Link Control and Status (LINKCTRLSTS_0_2_0_PCI) Device Capabilities 2 (DEVCAP2_0_2_0_PCI) Link Capabilities 2 (LINKCAP2_0_2_0_PCI) Message Signaled Interrupts Capability ID (MSI_CAPID_0_2_0_PCI) Message Control (MC_0_2_0_PCI) Message Address (MA0_0_2_0_PCI) Message Address (MA1_0_2_0_PCI) Message Data (MD_0_2_0_PCI) MSI Mask Bits (MSI_MASK_0_2_0_PCI) MSI Pending Bits (MSI_PEND_0_2_0_PCI) Power Management Capabilities ID (PMCAPID_0_2_0_PCI) Power Management Capabilities (PMCAP_0_2_0_PCI) Power Management Control and Status (PMCS_0_2_0_PCI) Graphics System Event (GSE_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI) Device 2 Mirror of Protected Audio Video Path Control (PAVPC1_0_2_0_PCI) Stepping Revision ID (SRID_0_2_0_PCI) ASL Storage (ASLS_0_2_0_PCI) ARI Extended Capability Header (ARI_CAPHDR_0_2_0_PCI) ARI Capability (ARI_CAP_0_2_0_PCI) ARI Control (ARI_CTRL_0_2_0_PCI) PASID Extended Capability Header (PASID_EXTCAP_0_2_0_PCI) PASID Capability (PASID_CAP_0_2_0_PCI) PASID Control (PASID_CTRL_0_2_0_PCI) ATS Extended Capability Header (ATS_EXTCAP_0_2_0_PCI) ATS Capability (ATS_CAP_0_2_0_PCI) ATS Control (ATS_CTRL_0_2_0_PCI) VF Resizable Capability Header (VF_RESIZE_CAPHDR_0_2_0_PCI) VF Resizable Capability (VF_RESIZE_CAP_0_2_0_PCI) VF Resizable Control (VF_RESIZABLE_CTRL_0_2_0_PCI) SRIOV Extended Capability Header (SRIOV_ECAPHDR_0_2_0_PCI) SRIOV Capabilities (SRIOV_CAP_0_2_0_PCI) SRIOV Control Register (SRIOV_CTRL_0_2_0_PCI) SRIOV Status (SRIOV_STS_0_2_0_PCI) SRIOV Initial VFs (SRIOV_INITVFS_0_2_0_PCI) SRIOV Total VFs (SRIOV_TOTVFS_0_2_0_PCI) Number Of VFs (SRIOV_NUMOFVFS_0_2_0_PCI) First VF Offset (FIRST_VF_OFFSET_0_2_0_PCI) VF Stride (VF_STRIDE_0_2_0_PCI) VF Device ID (VF_DEVICEID_0_2_0_PCI) Supported Page Sizes (SUPPORTED_PAGE_SIZES_0_2_0_PCI) System Page Sizes (SYSTEM_PAGE_SIZES_0_2_0_PCI) VF BAR0 Lower DWORD (VF_BAR0_LDW_0_2_0_PCI) VF BAR0 Upper DWORD (VF_BAR0_UDW_0_2_0_PCI) LTR Extended Capability Header (LTR_CAPHDR_0_2_0_PCI) Max Snoop Latency Register (MAX_SNP_LAT_0_2_0_PCI) Max No Snoop Latency Register (MAX_NOSNP_LAT_0_2_0_PCI) PF Resizable Capability Header (PF_RESIZE_CAPHDR_0_2_0_PCI) PF Resizable BAR Capability (PF_RESIZE_BAR_CAP_0_2_0_PCI) PF Resizable BAR Control (PF_RESIZABLE_BAR_CTRL_0_2_0_PCI)

Group Flags (GRPFLAGS3) – Offset 3e8

The Group Configuration Table is an array of registers in BAR0 that controls the mapping of work queues to engines. The offset of the Group Configuration Table is given by the Group Configuration Offset field in the Table Offsets register. The number of groups is given by the Number of Groups field in GRPCAP. Software may configure the number of groups that it needs. Group Configuration registers beyond the number of groups available are reserved and may not be implemented in hardware.
Each active group contains one or more work queues and one or more engines. Any unused group must have both the WQs field and the Engines field equal to 0. Descriptors submitted to any WQ in a group may be processed by any engine in the group. Each active work queue must be in a single group. (An active work queue is one for which the WQ Size field of the corresponding WQCFG register is non-zero.) Any engine that is not in a group is inactive. See #671116 section 3.4 for more information on engines and groups.
Each GRPCFG register is divided into three sub-registers.
These registers are read-write while the device is Disabled and read-only otherwise. They are read-only at all times if the Configuration Support field in GENCAP is 0.

Bit Range

Default

Access

Field Name and Description

63:38

0h

RO

Reserved

37:36

0h

RW/L

Batch Descriptors in Progress limit (BDIPL)

This field controls the number of batch descriptors that can be concurrently processed by an engine in the group as a fraction of the Maximum Batch Descriptors in Progress value specified in ENGCAP. Note that exercising this control can cause bandwidth to be reduced in some cases, depending on prevailing system latency. This field is reserved if the Descriptors in Progress Limit Supported field is GRPCAP is 0.
00: Allow up to the maximum value that an engine is capable of.
01: Limit to 1/2 of the maximum value.
10: Limit to 1/4 of the maximum value.
11: Limit to 1/8 of the maximum value.

35:34

0h

RO

Reserved

33:32

0h

RW/L

Work descriptors in progress limit (WDIPL)

This field controls the number of work descriptors that can be concurrently processed by an engine in the group as a fraction of the Maximum Work Descriptors in Progress value specified in ENGCAP. Note that exercising this control can cause bandwidth to be reduced in some cases, depending on prevailing system latency. This field is reserved if the Descriptors in Progress Limit Supported field is GRPCAP is 0.
00: Allow up to the maximum value that an engine is capable of.
01: Limit to 1/2 of the maximum value.
10: Limit to 1/4 of the maximum value.
11: Limit to 1/8 of the maximum value.

31:28

0h

RO

Reserved

27:20

0h

RO/V

Bandwidth Tokens Allowed (BWTOKALLOW)

This field indicates the maximum number of Read Buffers that may be in use at one time by all engines in the group. This value can be used to limit the maximum bandwidth used by engines in the group. This value must be:
- greater than or equal to 4 times the number of engines in the group;
- greater than or equal to the Read Buffers Reserved field for thisgroup; and
- less than or equal to the sum of the Read Buffers Reserved field andthe number of non-reserved Read Buffers.
(The number of non-reserved Read Buffers is the Total Read Buffers field in GRPCAP minus the total of the Read Buffers Reserved fields for all groups.)
The default value of this field is the same as the value of the Total Read Buffers field in GRPCAP.
If the Read Buffer Controls Supported field in GRPCAP is 0, this field is read-only and is unused.

19:16

0h

RO

Reserved

15:8

0h

RO

Bandwidth Tokens Reserved (BWTOKRSVD)

This field indicates the number of Read Buffers reserved for the use of engines in the group. This value can be used to reduce the possibility of contention with engines in other groups. However, if it is set to a nonzero value, it may reduce the overall performance of the device. The sum of the Read Buffers reserved for all groups must be less than or equal to the Total Read Buffers field in GRPCAP.
If the Read Buffer Controls Supported field in GRPCAP is 0, this field is read-only and is unused.

7

0h

RO

Use Global Bandwidth Token Limit (UGBTL)

0: The Global Read Buffer Limit does not apply to this group.
1: The Global Read Buffer Limit programmed in the GENCFG register applies to descriptors processed by engines in this group. (The limit indicated by the Read Buffers Allowed field applies as well.)
If the Global Read Buffer Limit Supported field in GRPCAP is 0, this field is reserved.

6

0h

RO

Reserved

5:3

0h

RW/L

GRPFLAGS TC-B (TCB)

Specifies the traffic class to use for memory accesses for which the traffic class selector in the descriptor is 1.

2:0

0h

RW/L

GRPFLAGS TC-A (TCA)

Specifies the traffic class to use for memory accesses for which the traffic class selector in the descriptor is 0.