Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 872351 | 04/14/2026 | 001 | Public |
General Configuration (GENCFG) – Offset 80
This register is read-write while the device is Disabled and read-only otherwise. It is read-only at all times if the Configuration Support field in GENCAP is 0.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:14 | 0h | RO | Reserved |
| 13 | 0h | RW/L | Event Log Enable (EVNTLOGEN) 0: Hardware writes any software error related events to SWERROR. |
| 12 | 0h | RW/L | User-mode Interrupts Enable (UMIE) 0: User-mode descriptors are not allowed to request completion interrupts. |
| 11:8 | 0h | RO | Reserved |
| 7:0 | 0h | RO/V | Global Bandwidth Token Limit (GBTL) This field indicates the maximum number of Read Buffers that may be in use at one time by operations that access low bandwidth memory. This number of Read Buffers is shared by all descriptors accessing low bandwidth memory across the entire device. The default value is equal to the Total Read Buffers reported in GRPCAP. |