63:55

0h

RO

Reserved

54

1h

RO/V

Strict Ordering limitation for peer destinations. (SOLPD)

0: Strict ordering is supported for descriptors whose destination address references a peer device.
1: The Strict Ordering flag is reserved in descriptors whose destination address references a peer device.

53

1h

RO/V

Strict Ordering limitation for memory destinations. (SOLMD)

0: Strict ordering is supported for descriptors whose destination address references memory.
1: The Strict Ordering flag is reserved in descriptors whose destination address references memory.

52:33

0h

RO

Reserved

32

0h

RO

Event Log Overflow Support (ELOS)

0: Event Log does not overflow. If the Event Log is full at the time hardware attempts to append an entry, the device blocks until the Event Log Head field is updated by software.
1: Event Log may overflow. If the Event Log is full at the time hardware attempts to append an entry, hardware drops the event, and attempts to log an error in SWERROR to indicate the Event Log full condition. If the Valid bit in SWERROR is 1 and the Event Log is full at the time an event occurs, the Overflow bit is SWERROR is set to 1.

31

1h

RO

Configuration Support (CS)

0: General Configuration, Group Configuration, and some fields of the Work Queue Configuration registers are read-only and reflect the fixed configuration of the device. See #341204 section 9.2.24 for details about which WQ configuration fields are read-only.
1: General Configuration, Group Configuration, and Work Queue Configuration registers are read-write and can be used by software to set the desired configuration.

30:25

0h

RO/V

Interrupt Message Storage Size (IMSS)

The number of entries in the Interrupt Message Storage is N × 256, where N is the value in this field. If the Interrupt Message Storage Support field in the Scalable IOV capability is 0, the value in this field is undefined.

24:21

0h

RO

Maximum Supported Batch Size (MSBS)

The maximum number of descriptors that can be referenced by a Batch descriptor is independently controlled for each WQ. This field indicates the maximum value that each WQ can be configured with. The maximum supported batch size is 2N, where N is the value in this field. If Batch descriptor is not supported (as indicated by bit 1 of OPCAP), this field is unused.

20:16

1fh

RO/V

Maximum Supported Transfer Size (MSTS)

The maximum transfer size that can be specified in a descriptor is independently controlled for each WQ. This field indicates the maximum value that each WQ can be configured with. The maximum supported transfer size is 2^N, where N is the value in this field.

15

0h

RO

Reserved

14:13

0h

RO/V

Event Log Support (ELS)

0: No Event Log Support.
1: 64-byte entries.
2: 128-byte entries.
3: 256-byte entries.
See #341204 section 5.9 for more information on Event Log.

12

1h

RO/V

Completion Record Fault Info Support (CMPLRECFAULTINFO)

0: Completion Record does not have a Fault Information field.
1: Completion Record has a Fault Information field as specified in #341204 section 8.2.3.

11

0h

RO

CRC64 Support (CRC64)

0: The CRC Size flag in a CRC Generation or Copy with CRC Generation descriptor is not supported.
1: The CRC Size flag in a CRC Generation or Copy with CRC Generation descriptor is supported.

10

1h

RO

Fill16 Support (FILL16)

0: The Pattern Size flag in a Fill or Inter-Domain Memory Fill descriptor is not supported.
1: The Pattern Size flag in a Fill or Inter-Domain Memory Fill descriptor is supported.

9

0h

RO/V

Drain Descriptor Readback Address Support (DDRAS)

0: Hardware does not support specification of Readback Addresses in Drain descriptors and the Readback Address Valid flags and the Readback Address fields in the descriptor are reserved.
1: Hardware supports specification of Readback Addresses in Drain descriptors. If the corresponding Readback Address Valid flags are set, hardware will issue the corresponding readbacks.

8

0h

RO/V

Destination Readback Support (DR)

0: The Destination Readback flag in descriptors is not supported.
1: The Destination Readback flag in descriptors is supported

7

0h

RO/V

Translation Fetch Stride Support (TRANSLATIONFETCHSTRIDE)

0: The Use Stride flag in a Translation Fetch descriptor is not supported. Hardware uses an implementation specific stride value.
1: The Use Stride flag in a Translation Fetch descriptor is supported.

6

0h

RO

Inter-Domain Support (INTERDOMAINSUPP)

0: Inter-Domain operations are not supported.
1: Inter-Domain operations are supported while the PASID capability is enabled. Inter-Domain capabilities are reported in the IDCAP register (#341204 section 9.2.18).

5

0h

RO

Reserved

4

1h

RO/V

Admin Command Capabilities Support (ACCS)

0: The Command Capabilities register is not supported. The administrative commands supported are listed in #341204 Table 9-6.
1: The Command Capabilities register is supported and reports the set of administrative commands supported by the device. See #341204 section 9.2.14 for a description of the Command Capabilities register.

3

0h

RO

Reserved

2

0h

RO/V

Cache Control Support (Memory) (CCSM)

0: Cache control for memory write operations is not supported. The Cache Control flag in descriptors that write to memory is reserved.
1: Cache control for write operations is supported. Software can use the Cache Control flag in descriptors to control the use of cache.

1

0h

RO

Overlapping Copy Support (OCS)

0: Overlapping copies are not supported. If source and destination buffers overlap, it is an error.
1: Overlapping copies are supported by the Memory Move operation. See the description of the Memory Move operation for details of the behavior.Regardless of the value of this field, overlapping copies are not supported by any operation other than Memory Move.

0

1h

RO/V

Block on Fault Support (BOFS)

0: Block on fault is not supported. The Block On Fault Enable bit in the WQCFG registers and the Block On Fault flag in descriptors are reserved. If a page fault occurs on a source or destination memory access, the operation stops and the page fault is reported to software.
1: Block on fault is supported. Behavior on page faults depends on the values of the Block On Fault Enable bit in each WQCFG register and the Block on Fault flag in each descriptor.See #341204 section 3.13 for more information on page fault handling.