Command (CMD) – Offset a0 - 001 - ID:872351 | Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers

Introduction
D0:F0 Host Bridge and DRAM Controller - GTTMMADR
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 1)
D0:F0 Host Bridge and DRAM Controller - Host Bridge/DRAM (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 1)
- VTDs Range Base Address Register (VTDBAR_0_0_0_MCHBAR_NCU)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Host Controller (part 2)
- CAPID0_F PCI (CAPID0_F_0_0_0_PCI)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 1)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 2)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 3)
- Rank Temperature (RANK_TEMPERATURE_0_0_0_MCHBAR)
- PM CONFIG THERM STATUS 0 0 0 MCHBAR (PM_CONFIG_THERM_STATUS_0_0_0_MCHBAR)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 4)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Memory Controller (part 5)
D0:F0 Host Bridge and DRAM Controller - MCHBAR Power Management
D0:F0 Host Bridge and DRAM Controller - VTDPVC0BAR
D10:F0 Platform Monitoring Technology (PMT) Registers
D11:F0 Vision Processing Unit
D2:F0 Processor Graphics
D4:F0 Dynamic Tuning Technology
D5:F0 Image Processing Unit

Command (CMD) – Offset a0

The Command register is used to submit administrative commands. Before writing to this register, software must ensure that any command previously submitted via this register has completed by checking the Active field of the Command Status register. When a command is submitted, the Active field of the Command Status register is set to 1. The Active field changes to 0 when the command is complete. The other fields of the Command Status register indicate whether the command completed successfully. If the command register is written while Active is 1, the value written is discarded and an error is recorded in the SWERROR register. Reading the Command register returns unpredictable values.

Bit Range	Default	Access	Field Name and Description
31	0h	RW/V	Request Completion Interrupt (RCI) When this field is 1, upon completion of the command an interrupt is generated using entry 0 in the MSI-X table.
30:25	0h	RO	Reserved
24:20	0h	RW/V	Command Code (CC) See #341204 Table 9-5 for command codes. Undefined command codes are reserved.
19:0	0h	RW/V	CMD Operand (OP) The meaning of this field depends on the command. See #341204 Table 9-5.

Command Status (CMDSTATUS)

Interrupt Cause (INTCAUSE) Command Status (CMDSTATUS)