15:11

0h

RO

Reserved

10

0h

RO

Interrupt Disable (INTD)

Controls the ability of the Function to generate INTx interrupts. This Function does not generate INTx interrupts, so this bit it hardwired to 0b.

9

0h

RO

Fast Back-to-Back Enable (FBE)

Does not apply to PCI Express and is hardwired to 0b

8

0h

RW

SERR Enable (SEE)

When Set, this bit enables reporting of Non-Fatal and Fatal errors detected by the Function to the Root Complex.
Note that errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control register

7

0h

RO

Wait Cycle Control (WCC)

Does not apply to PCI Express and is hardwired to 0b

6

0h

RW

Parity Error Response Enable (PERE)

This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register.

5

0h

RO

VGA Palette Snoop Enable (VGAPSE)

Does not apply to PCI Express and is hardwired to 0b

4

0h

RO

Memory Write and Invalidate Enable (MWIE)

Does not apply to PCI Express and is hardwired to 0b

3

0h

RO

Special Cycle Enable (SCE)

Does not apply to PCI Express and is hardwired to 0b

2

0h

RW

Bus Master Enable (BME)

Controls the ability of the endpoint to issue Memory Read/Write requests.

When set, the Function is allowed to issue Memory Requests.
When clear, the Function is not allowed to issue Memory Requests.
Note that as MSI-X interrupt Messages are in-band memory writes, setting BME to 0b disables MSI-X interrupt Messages as well.
Requests other than Memory Requests (eg Completion) are not controlled by this bit.
See the RAS Chapter in the HAS for programming restrictions.

1

0h

RW

Memory Space Enable (MSE)

Controls the Function response to Memory Space accesses.
A value of 0 disables the response. A value of 1 allows the Function to respond to Memory Space accesses.

0

0h

RO

I/O Space Enable (IOSE)

Controls the Function response to I/O Space accesses.
A value of 0 disables the response. Hardwired to 0 as this Function does not support I/O Space accesses.