Intel® Core™ Ultra Series 3 Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 872351 | 04/14/2026 | 001 | Public |
WQ Configuration G (WQCFGG5) – Offset 558
WQ Configuration G
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:30 | 0h | RO/V | WQ State (STATE) 00: WQ is Disabled. Descriptors are not accepted into the WQ. (ENQ operations to this WQ return Retry. Other write operations are ignored.) |
| 29 | 0h | RO/V | WQ Mode Support (MODE) When the Configuration Support field in GENCAP is 0, this field indicates whether certain WQ configuration fields are read-only. See the table in #341204 for the meaning of this field. When the Configuration Support field in GENCAP is 1, this field is unused. |
| 28:17 | 0h | RO | Reserved |
| 16 | 0h | RW/1C/V | WQ Occupancy Interrupt Generated (OCCINTGEN) 0: There are no WQ Occupancy Interrupts for this WQ that have not been acknowledged by software. Device is able to generate a WQ Occupancy Interrupt if the conditions are satisfied. |
| 15:0 | 0h | RO/V | WQ Occupancy (OCC) The number of entries currently in this WQ. This number may change whenever descriptors are submitted to or dispatched from the queue, so it cannot be relied on to determine whether there is space in the WQ.If the WQ Occupancy Support field in WQCAP is 0, the value in this field is undefined. |