31:26

0h

RW/V

Memory Base Address (MBA_​0)

Set by the OS, these bits correspond to address signals [63:24].

25

0h

RW/V

Memory Base Address Tile 1 (MBAT_​1)

Set by the OS, these bits correspond to address signals [25:24]. The accessibility of these registers is governed by the tile count. If 1 tile, then these are R/W. If 2 tiles, then bit 24 is RO=0, bit 25 is R/W. If 4 tiles, then bits 25:24 are RO=0. On an FLR, bits 25:24 should be cleared to defaults (2'b0)

24

0h

RW/V

Memory Base Address Tile 0 (MBAT_​0)

Set by the OS, these bits correspond to address signals [25:24]. The accessibility of these registers is governed by the tile count. If 1 tile, then these are R/W. If 2 tiles, then bit 24 is RO=0, bit 25 is R/W. If 4 tiles, then bits 25:24 are RO=0. On an FLR, bits 25:24 should be cleared to defaults (2'b0)

23:4

0h

RO

Address Mask (ADM)

Hardwired to 0s to indicate at least 16MB address range.

3

1h

RO/V

Prefetchable Memory (PREFMEM)

Default to 1 to indicate prefetchable.

2:1

2h

RO

Memory Type (MEMTYP)

Hardwired to 2h to indicate 64 bit base address.

0

0h

RO

Memory I/O Space (MIOS)

Hardwired to 0 to indicate memory space.