15

0h

RW/1C/V

Detected Parity Error (DPE)

This bit is Set by a Function whenever it receives a Poisoned TLP, regardless of the state the Parity Error Response bit in the Command register.

14

0h

RW/1C/V

Signaled System Error (SSE)

This bit is Set when a Function sends an ERR_​FATAL or ERR_​NONFATAL Message, and the SERR Enable bit in the Command register is 1.

13

0h

RW/1C/V

Received Master Abort (RMA)

This bit is Set when a Requester receives a Completion with Unsupported Request Completion Status.

12

0h

RW/1C/V

Received Target Abort (RTA)

This bit is Set when a Requester receives a Completion with Completer Abort Completion Status.

11

0h

RW/1C/V

Signaled Target Abort (STA)

This bit is Set when a Function completes a Posted or Non-Posted Request as a Completer Abort error.

10:9

0h

RO

DEVSEL Timing (DT)

Does not apply to PCI Express and is hardwired to 00b

8

0h

RW/1C/V

Master Data Parity Error (MDPE)

This bit is Set by an Endpoint Function if the Parity Error Response bit in the Command register is 1b it either receives a Poisoned Completion or transmits a Poisoned Request

7

0h

RO

Fast Back-to-Back Transactions Capable (FBTC)

Does not apply to PCI Express and is hardwired to 0b

6

0h

RO

Reserved

5

0h

RO

66 MHz Capable (C66)

Does not apply to PCI Express and is hardwired to 0b

4

1h

RO

Capabilities List (CL)

Indicates the presence of an Extended Capability list item. Required by all PCI Express endpoints.

3

0h

RO

Interrupt Status (INTS)

When Set, indicates that an INTx emulation interrupt is pending internally in the Function. Hardwired to 0b as this Function does not support INTx

2:0

0h

RO

Reserved