Peripheral Channel (Channel 0) Overview

The Peripheral channel performs the following functions:

• Target for PCI Device: The eSPI controller duplicates the legacy LPC PCI Configuration space registers. These registers are mostly accessed via the BIOS, though some are accessed via the OS as well.
• Tunnel all Host to eSPI device (EC/SIO) Debug Device Accesses: These are the accesses that used to go over the LPC bus. These include various programmable and fixed I/O ranges as well as programmable Memory ranges. The programmable ranges and their enables reside in the PCI Configuration space.
• Tunnel all Accesses from the eSPI device to the Host: These include Memory Reads and Writes.

Virtual Wire Channel (Channel 1) Overview

The Virtual Wire channel uses a standard message format to communicate several types of signals between the components on the platform.

• Sideband and GPIO Pins: System events and other dedicated signals between the processor and eSPI device. These signals are tunneled between the 2 components over eSPI.
• Serial IRQ Interrupts: Interrupts are tunneled from the eSPI device to the processor. Both edge and triggered interrupts are supported.

• eSPI Virtual Wires (VW)

  Table below summarizes the virtual wires in eSPI mode.

  eSPI Virtual Wires (VW)

  Virtual Wire	processor Pin Direction	Reset Control	Pin Retained in processor (For Use by Other Components)
  SUS_​STAT#	Output	ESPI_​RESET#	No
  PRIM_​PWRDN_​ACK	Output	ESPI_​RESET#	No
  SUSWARN#	Output	ESPI_​RESET#	No
  SUS_​ACK	Input	ESPI_​RESET#	No
  PLTRST#	Output	ESPI_​RESET#	Yes
  PME# (eSPI Peripheral PME)	Input	ESPI_​RESET#	N/A
  WAKE#	Input	ESPI_​RESET#	No
  SMI#	Input	PLTRST#	N/A
  SCI#	Input	PLTRST#	N/A
  RCIN#	Input	PLTRST#	No
  SLP_​A#	Output	ESPI_​RESET#	Yes
  SLP_​S3#/SLP_​S4#/SLP_​S5#/SLP_​LAN#/SLP_​WLAN#	Output	RSMRST#	Yes
  DEVICE_​BOOT_​LOAD_​DONE	Input	ESPI_​RESET#	N/A
  DEVICE_​BOOT_​LOAD_​STATUS	Input	ESPI_​RESET#	N/A
  HOST_​RST_​WARN	Output	PLTRST#	N/A
  HOST_​RST_​ACK	Input	PLTRST#	N/A
  OOB_​RST_​WARN	Output	ESPI_​RESET#	N/A
  OOB_​RST_​ACK	Input	ESPI_​RESET#	N/A
  HOST_​C10	Output	PLTRST#	N/A
  ERROR_​NONFATAL	Input	ESPI_​RESET#	N/A
  ERROR_​FATAL	Input	ESPI_​RESET#	N/A
  DNX_​WARN	Output	PLTRST#	N/A
  DNX_​ACK	Input	ESPI_​RESET#	N/A

• Interrupt Events

  eSPI supports both level and edge-triggered interrupts. Refer to the eSPI Specification for details on the theory of operation for interrupts over eSPI.

  The eSPI controller will issue a message to the interrupt controller when it receives an IRQ group in its VW packet, indicating a state change for that IRQ line number.

  The eSPI device can send multiple VW IRQ index groups in a single eSPI packet, up to the Operating Maximum VW Count programmed in its Virtual Wire Capabilities and Configuration Channel.

  The eSPI controller acts only as a transport for all interrupt events generated from the device. It does not maintain interrupt state, polarity or enable for any of the interrupt events.

Out-of-Band Channel (Channel 2) Overview

The Out-of-Band channel performs the following functions:

• Tunnel MCTP Packets between the Intel^® CSME and eSPI Device: The Intel^® CSME communicates MCTP messages to/from the device by embedding those packets over the eSPI protocol. This eliminates the SMBus connection between the processor and the device which was used to communicate the MCTP messages. The eSPI controller simply acts as a message transport and forwards the packets between the Intel^® CSME and eSPI device.
• Tunnel Processor Temperature Data to the eSPI device: The eSPI controller stores the processor temperature data internally and sends it to the device using a posted OOB message when a request is made to a specific destination address.
• Tunnel Processor RTC Time and Date Bytes to the eSPI device: the eSPI controller captures this data internally at periodic intervals from the processor RTC controller and sends it to the device using a posted OOB message when a request is made to a specific destination address.

• Processor Temperature Data Over eSPI OOB Channel

  eSPI controller supports the transmitting of processor thermal data to the eSPI device. The thermal data consists of 1 byte of processor temperature data that is transmitted periodically (~1 ms) from the thermal sensor unit.

  The packet formats for the temperature request from the eSPI device and the processor response back are shown in the two figures below.

  eSPI Device Request to Processor for Processor Temperature

  Processor Response to eSPI device with Processor Temperature

• Processor RTC Time/Date to EC Over eSPI OOB Channel

  The processor eSPI controller supports the transmitting of processor RTC time/date to the eSPI device. This allows the eSPI device to synchronize with the Processor RTC system time. Moreover, using the OOB message channel allows reading of the internal time when the system is in Sx states.

  The RTC time consists of 7 bytes: seconds, minutes, hours, day of week, day of month, month and year. The controller provides all the time/date bytes together in a single OOB message packet. This avoids the boundary condition of possible roll over on the RTC time bytes if each of the hours, minutes, and seconds bytes is read separately.

  The packet formats for the RTC time/date request from the eSPI device and the processor response back to the device are shown in the two figures below.

  eSPI Device Request to Processor for Processor RTC Time

  Processor Response to eSPI device with RTC Time

  Notes:

  1. DS: Daylight Savings. A 1 indicates that Daylight Saving has been comprehended in the RTC time bytes. A 0 indicates that the RTC time bytes do not comprehend the Daylight Savings.
  2. HF: Hour Format. A 1 indicates that the Hours byte is in the 24-hr format. A 0 indicates that the Hours byte is in the 12-hr format. In 12-hr format, the seventh bit represents AM when it is a 0 and PM when it is a 1.
  3. DM: Data Mode. A 1 indicates that the time byte are specified in binary. A 0 indicates that the time bytes are in the Binary Coded Decimal (BCD) format.

Flash Access Channel (Channel 3) Overview

The Flash Access channel supports the Host Attached Flash (MAF) configuration, where the flash device is directly attached to the processor. This configuration allows the eSPI device to access the flash device attached to the processor through a set of flash access commands. These commands are routed to the flash controller and the return data is sent back to the eSPI device.

The Host Attached Flash Channel controller (MAFCC) tunnels flash accesses from eSPI device to the flash controller. The MAFCC simply provides Flash Cycle Type, Address, Length, Payload (for writes) to the flash controller. The flash controller is responsible for all the low level flash operations to perform the requested command and provides a return data/status back to the MAFCC, which then tunnels it back to the eSPI device in a separate completion packet.

• Host Attached Flash Channel Controller (MAFCC) Flash Operations and Addressing

  The EC is allocated a dedicated region within the eSPI Host-Attached flash device. The EC has default read, write, and erase access to this region.

  The EC can also access any other flash region as permitted by the Flash Descriptor settings. As such, the EC uses linear addresses, valid up to the maximum supported flash size, to access the flash.

  The MAFCC supports flash read, write, and erase operations only.

• Device Attached Flash Channel Controller (SAFCC) Flash Operation and Addressing

  The processor is allocated dedicated regions (for each of the supported Controllers) within the eSPI SAFCC. The processor has read, write, and erase access to these regions, as well as any other regions that maybe permitted by the region protections set in the Flash Descriptor.

  The Device will optionally perform additional checking on the processor provided address. In case of an error due to incorrect address or any other issues it will synthesize an unsuccessful completion back to the eSPI Host.

  The SAFCC supports Flash Read, Write and Erase operations. It also supports Read SFDP and Read JEDEC ID commands as specified in the eSPI Specification for Server platforms.