SAGV Points

Intel® Core™ Ultra 200H and 200U Series Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
842704	05/27/2025		Public

SAGV (System Agent Geyserville) is a way by which the SOC can dynamically scale the work point (V/F), by applying DVFS (Dynamic Voltage Frequency Scaling) based on memory bandwidth utilization and/or the latency requirement of the various workloads for better energy efficiency at System-Agent. Pcode heuristics are in charge of providing request for Qclock work points by periodically evaluating the utilization of the memory and IA stalls.

SA Speed Enhanced Speed Steps (SA-GV) and Gear Mode Frequencies

Processor	Technology	DDR Maximum Rate [MT/s]	SAGV-LowBW	SAGV-MedBW	SAGV-HighBW	SAGV- High Performance
H/U	LPDDR5x	8400	3200 G4	4800 G4	6400 G4	8400 G4
H/U	LPDDR5x	7466	3200 G4	4800 G4	6400 G4	7466 G4
U	DDR5	6400	3200 G4	4800 G4	6400 G4	5600 G2
U	DDR5	5600	3200 G4	4800 G4	5200 G4	5600 G2
H	DDR5	6400	3200 G4	4800 G4	6000 G4	6400 G2
H	DDR5	5600	3200 G4	4800 G4	5200 G4	5600 G2
Notes: Intel® Core Ultra 200H and 200U Series Processors supports dynamic gearing technology where the Memory Controller can run at 1:2 (Gear-2 mode) or 1:4 (Gear-4 mode) ratio of DRAM speed. The gear ratio is the ratio of DRAM speed to Memory Controller Clock . MC Channel Width equal to DDR Channel width multiply by Gear Ratio. Frequency points may change depending on system validation. SA-GV modes: LowBW- Low frequency point, Minimum Power point. Characterized by low power, low BW, high latency. The system will stay at this point during low to moderate BW consumption. MedBW - Tuned for balance between power & performance. HighBW - Characterized by high power, low latency, moderate BW also used as RFI mitigation point. MaxBW/Lowest latency Lowest Latency point, low BW and highest power.

DDR Frequency Shifting

DDR interfaces emit electromagnetic radiation which can couple to the antennas of various radios that are integrated in the system, and cause radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR5 and LPDDR5/x technologies for the Wi-Fi* high and ultra-high bands (~5-7 GHz) . By changing the DDR data rate, the harmonics of the clock can be shifted out of a radio band of interest, thus mitigating RFI to that radio. This feature is working with SAGV on, one of the SAGV points is used as RFI mitigation point.