Intel® Core™ Ultra 200H and 200U Series Processors
Datasheet, Volume 1 of 2
P-core, E-core, and LP E-core Level 0, Level 1 and Level 2 Caches
U-Processor Series
The 1st level caches are not shared between physical cores and each physical core has a separate set of caches.
The P-Core 1st level cache hierarchy is divided into:
On the data side, it is built as one-level cache, with L1 of 48KB, 12-way set-associative.
On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.
The E-Core 1st level cache hierarchy is divided into:
On the data side, it is built as one-level cache, with L1 of 32KB, 8-way set-associative.
On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.
The LP E-Core 1st level cache hierarchy is divided into:
On the data side, it is built as one-level cache, with L1 of 32KB, 8-way set-associative.
On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.
The 2nd level cache holds both data and instructions. It is also referred to as mid-level cache or MLC.
- The P-core 2nd level caches are not shared between physical cores and each physical core has a separate set of caches. Its size is 2MB and it is a 16-way associative non-inclusive cache.
- The E-core 2nd level cache is shared between E-Cores within a module of 4 E-Cores in the Compute tile. Its size is 2MB and it is a 16-way associative non-inclusive cache.
- The LP E-core 2nd level cache is shared between LP E-Cores within a module of 2 LP E-Cores in the SOC tile. Its size is 2MB and it is a 16-way associative non-inclusive cache.
U-Processor P-core, E-core, and LP E-core Cache Hierarchy
| Cache | P-core | E-Core | LP E-core |
|---|---|---|---|
| L1 D L1 | 48KB 12-way set-associative per core | 32KB 8-way set-associative per core | 32KB 8-way set-associative per core |
| L1 I L1 | 64KB 16-way set-associative per core | 64KB 16-way set-associative per core | 64KB 16-way set-associative per core |
| L2 | 2MB 16-way set-associative per core | 2MB 16-way set-associative within a module of 4 Compute tile E-cores | 2MB 16-way set-associative within a module of 2 SOC tile LP E-cores |
| L3 | Maximum of 3 MB per P-core / module of 4 E-cores shared across Compute tile | None | |
H-Processor Series
The 1st level caches are not shared between physical cores and each physical core has a separate set of caches.
The P-Core 1st level cache hierarchy is divided into:
On the data side, it is built as two-level cache, with L0 of 48KB and L1 of 192KB, both of which are 12-way set-associative.
On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.
The E-Core 1st level cache hierarchy is divided into:
On the data side, it is built as one-level cache, with L1 of 32KB, 8-way set-associative.
On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.
The LP E-Core 1st level cache hierarchy is divided into:
On the data side, it is built as one-level cache, with L1 of 32KB, 8-way set-associative.
On the instruction side, there is a single L1 cache of 64KB, which is 16-way set associative.
The 2nd level cache holds both data and instructions. It is also referred to as mid-level cache or MLC.
- The P-core 2nd level caches are not shared between physical cores and each physical core has a separate set of caches. Its size is 3MB and it is a 12-way associative non-inclusive cache.
- The E-core 2nd level cache is shared between E-Cores within a module of 4 E-Cores in the Compute tile. Its size is 4MB and it is a 16-way associative non-inclusive cache.
- The LP E-core 2nd level cache is shared between LP E-Cores within a module of 2 LP E-Cores in the SOC tile. Its size is 2MB and it is a 16-way associative non-inclusive cache.
H-Processor P-core, E-core, and LP E-core Cache Hierarchy
| Cache | P-core | E-core | LP E-core |
|---|---|---|---|
| L0 DL0 | 48KB 12-way set-associative per core | None | None |
| L1 DL1 | 192KB 12-way set-associative per core | 32KB 8-way set-associative per core | 32KB 8-way set-associative per core |
| L1 IL1 | 64KB 16-way set-associative per core | 64KB 16-way set-associative per core | 64KB 16-way set-associative per core |
| L2 | 3MB 12-way set-associative per core | 4MB 16-way set-associative within a module of 4 Compute tile E-cores | 2MB 16-way set-associative within a module of 2 SOC tile LP E-cores |
| L3 | Maximum of 3 MB per P-core / module of 4 E-cores shared across Compute tile | None | |