Functional Description

The main blocks of the integrated Connectivity solution are partitioned according to the following:

• Connectivity Controller IP contains:
  • Interfaces to the processor
  • Debug and testing interfaces
  • Power management and clock Interfaces
  • Interface to the Companion RF module (CRF)
  • Interface to physical I/O pins controlled by the processor.
  • Interfaces to the LTE modem via processor GPIO
• Companion RF (CRF): This is the integrated connectivity M.2 module. The CRF Top contains:
  • Debug and testing interfaces
  • Power and clock Interfaces
  • Interface to the Connectivity Controller chip
• Physical I/O Pins: The SCU units are responsible for generating and controlling the power and clock resources of Connectivity Controller and CRF. There are unique SCUs in Connectivity Controller and CRF and their operation is coordinated due to power and clock dependencies. This coordination is achieved by signaling over a control bus (AUX) connecting Connectivity Controller and CRF.

Both Connectivity Controller and CRF have a dedicated AUX bus and arbiter. These two AUX buses are connected by a special interface that connects over the RGI bus. Each of the Connectivity Controller and CRF cores is dedicated to handle a specific connectivity function (Wi-Fi, Bluetooth).

Only the digital part of the connectivity function is located in Connectivity Controller cores, while the CRF cores handle some digital, but mostly analog and RF functionality. Each core in the Connectivity Controller has an interface to the host and an interface to its counterpart in CRF. CRF cores include an analog part which is connected to board level RF circuitry and to an antenna.

The H-Processor CNVi Controller supports both CNVio2 and CNVio3 also called as STEP (Serial Time Encoded Protocol) interface for Wi-Fi 7 support. The CNVio interface has two data lanes and one clock for each direction. The CNVio3 uses the same clock signals of CNVio2 and does not use the CNVio2 data signals.

CNVio3, or STEP, is a new proprietary differential interface to support Wi-Fi 7 throughput requirements. CNVio3 is a serial digital interface and operates at 12 Gbits/sec.

CNVio3 reuses CNVio2 clock traces (1 TX clock and 1 RX clock). CNVio3 maps 2 bits symbols into pulse width. CNVio3 Transmit output is a PWM signal. Each 2 bits symbols have a positive pulse and a negative pulse. The transmission starts with positive pulse, and polarity is switched for every 2 bits symbols.CNVio3 Receive decodes the pulse width back into the transmitted symbols.