Signal Description

Intel® Core™ Ultra 200H and 200U Series Processors

Datasheet, Volume 1 of 2

ID	Date	Version	Classification
842704	05/27/2025		Public

Signal Name	Type	SSC Capable	Description	Availability
CLKOUT_GEN4_N[5:0] CLKOUT_GEN4_P[5:0] CLKOUT_GEN5_N6 CLKOUT_GEN5_P6 CLKOUT_GEN4_N[8:7] CLKOUT_GEN4_P[8:7]	O	Yes	*PCI Express Clock Output*: Serial Reference 100 MHz PCIe specification compliant differential output clocks to PCIe* devices	U/H
GPP_D04/IMGCLKOUT0/USB-C_GPP_D04 GPP_D00/IMGCLKOUT1/USB-C_GPP_D00 GPP_F07/RSVD/IMGCLKOUT2/USB-C_GPP_F07 GPP_F08/RSVD/IMGCLKOUT3/USB-C_GPP_F08 GPP_D07/IMGCLKOUT4/ISH_UART0_RTS#/ISH_SPI_MISO/USB-C_GPP_D07	O		Imaging Clock : Clock for external camera sensor.	U/H
GPP_C09/SRCCLKREQ0#/USB-C_GPP_C09 GPP_C10/SRCCLKREQ1#/USB-C_GPP_C10 GPP_C11/SRCCLKREQ2#/USB-C_GPP_C11 GPP_C12/SRCCLKREQ3#/USB-C_GPP_C12 GPP_C13/SRCCLKREQ4#/USB-C_GPP_C13 GPP_D21/RSVD/SRCCLKREQ5#/USB-C_GPP_D21	IOD		Clock Request: Serial Reference Clock request signals for PCIe* 100 MHz differential clocks	U/H
GPP_D18/SRCCLKREQ6#/USB-C_GPP_D18 GPP_D19/SRCCLKREQ7#/USB-C_GPP_D19 GPP_D20/SRCCLKREQ8#/USB-C_GPP_D20	IOD			U/H
XTAL_IN	I		Crystal Input: Input connection for 38.4 MHz crystal to Processor	U/H
XTAL_OUT	O		Crystal Output: Output connection for 38.4 MHz crystal to Processor	U/H
CLK_S_RCOMP CLK_I_RCOMP	Analog		Differential Clock Bias Reference: Used to set BIAS reference for differential clocks.	U/H
Notes: SSC = Spread Spectrum Clocking. Intel does not recommend changing the Plan of Record and fully validated SSC default value set in BIOS Reference Code. The SSC level must only be adjusted for debugging or testing efforts and any Non POR configuration setting used are the sole responsibility of the customer. U-Series Processor: SRCCLKREQ#[5:0] signals can be configured to map to any of the PCIe Lanes 1-12 while using clock output differential pairs CLKOUT_GEN4_P/N[5:0]. SRCCLKREQ#[8:6] signals can be configured to map to any of the PCIe Lanes 13-20 while using clock output differential pairs CLKOUT_GEN5_P/N[6] or CLKOUT_GEN4_P/N[8:7]. H-Series Processor: SRCCLKREQ#[5:0] signals can be configured to map to any of the PCIe Lanes 1-12 while using clock output differential pairs CLKOUT_GEN4_P/N[5:0]. SRCCLKREQ#[8:6] signals can be configured to map to any of the PCIe Lanes 13-28 while using clock output differential pairs CLKOUT_GEN5_P/N[6] or CLKOUT_GEN4_P/N[8:7]. Applicable to Gen5 PCIe Devices only: SRCCLKREQ#[8:6] signals can be configured to map to any of the PCIe Lanes 21-28 while using clock output differential pair CLKOUT_GEN5_P/N[6].