Intel® Core™ Ultra 200H and 200U Series Processors
Datasheet, Volume 1 of 2
| ID | Date | Version | Classification |
|---|---|---|---|
| 842704 | 05/27/2025 | Public |
Signal Description
| Signal Name | Type | Description | Availability |
|---|---|---|---|
| PCIE_5_TXP/GbE_TXP PCIE_5_TXN/GbE_TXN | O | Differential transmit pairs to the Intel® Ethernet Connection I219 based on the PCIe interface. Refer to PCI Express* (PCIe*) for details on the PCI Express*transmit signals. | H |
| PCIE_5_RXP/GbE_RXP PCIE_5_RXN/GbE_RXN | I | Differential receive pairs to the Intel® Ethernet Connection I219 based on the PCIe interface. Refer to PCI Express* (PCIe*) for details on the PCI Express* transmit signals. | H |
| GPP_C04/SML0DATA/USB-C_GPP_C04 | I/OD | System Management Link data signal interface to Intel® Ethernet Connection I219. Refer to System Management Interface and SMLink for details on the SML0DATA signal. | All Processor Series |
| GPP_C03/SML0CLK/USB-C_GPP_C03 | I/OD | System Management Link data signal interface to Intel® Ethernet Connection I219. Refer to System Management Interface and SMLink for details on the SML0CLK signal. | All Processor Series |
| GPP_V11/LANPHYPC | O | LAN PHY Power Control: LANPHYPC should be connected to LAN_DISABLE_N on the PHY. Processor will drive LANPHYPC low to put the PHY into a low power state when functionality is not needed. | H |
| GPP_V12/SLP_LAN# | IO | (H LAN Sub-System Sleep Control: If the Gigabit Ethernet Controller is enabled, when SLP_LAN# is de-asserted it indicates that the PHY device must be powered. When SLP_LAN# is asserted, power can be shut off to the PHY device. | H |
| GPP_V02/SOC_WAKE# | I | SOC_WAKE: LAN Wake Indicator from the GbE PHY. | H |