Intel® Core™ Ultra 200H and 200U Series Processors
Datasheet, Volume 1 of 2
System Power Supplies, Planes, and Signals
Power Plane Control
The SLP_S4# or SLP_S5# output signal can be used to cut power to the system core supply, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard.
The SLP_S4# output signal is used to remove power to additional subsystems that are powered during SLP_S3#, as well as power to the system memory, since the context of the system is saved on the disk. Cutting power to the memory may be done using the power supply, or by external FETs on the motherboard.
SLP_S5# output signal can be used to cut power to the system core supply.
SLP_A# output signal can be used to cut power to the Intel® Converged Security and Management Engine and SPI flash on a platform that supports the M3 state (for example, certain power policies in Intel® AMT).
SLP_LAN# output signal can be used to cut power to the external Intel® GbE PHY device.
SLP_S4# and Suspend-to-RAM Sequencing
The system memory suspend voltage regulator is controlled by the Glue logic. The SLP_S4# signal should be used to remove power to system memory rather than the SLP_S5# signal. The SLP_S4# logic in the processor provides a mechanism to fully cycle the power to the DRAM and/or detect if the power is not cycled for a minimum time.
PLT_PWROK Signal
When asserted, PLT_PWROK is an indication to the processor that its core well power rails are powered and stable. PLT_PWROK can be driven asynchronously. When PLT_PWROK is low, the processor asynchronously asserts PLTRST#. PLT_PWROK must not glitch, even if RSMRST# is low.
It is required that the power associated with PCIe* have been valid for 99 ms prior to PLT_PWROK assertion in order to comply with the 100 ms PCIe* 2.0 specification on PLTRST# de-assertion.
BATLOW# (Battery Low)
The BATLOW# input can inhibit waking from S4, S5 if there is not sufficient power. It also causes an SMI if the system is already in an S0 state.
SLP_LAN# Pin Behavior
The processor controls the voltage rails into the external LAN PHY using the SLP_LAN# pin.
- The LAN PHY is always powered when the Host and Intel® CSME systems are running.
- If the LAN PHY is required by Intel® CSME in Sx/M-Off, Intel® CSME must configure SLP_LAN#=’1’ irrespective of the power source and the destination power state. Intel® CSME must be powered at least once after G3 to configure this.
- If the LAN PHY is required after a G3 transition, the host BIOS must set AG3_PP_EN.
- If the LAN PHY is required in Sx/M-Off, the host BIOS must set SX_PP_EN.
- If the LAN PHY is not required if the source of power is battery, the host BIOS must set DC_PP_DIS.
SLP_WLAN# Pin Behavior
The processor controls the voltage rails into the external wireless LAN PHY using the SLP_WLAN# pin.
- The wireless LAN PHY is always powered when the Host is running.
- If Wake on Wireless LAN (WoWLAN) is required from S4/S5 states, the host BIOS must set HOST_WLAN_PP_EN.
- If Intel® CSME has access to the Wireless LAN device:
Intel® CSME configuration of SLP_WLAN# in Sx/M-Off is dependent on Intel® CSME power policy configuration.
When the Wireless LAN device is an integrated connectivity device (CNVi) the power to the CNVi external RF chip (CRF) must be always on. In this case the SLP_WLAN# shall not control the CRF 3.3 V power rail.
Below table summarizes
| Pin | GPP_A02 Input/Output (Determine by GP_IO_SEL bit) | Pin Value in S0 | Pin Value in Sx/M-Off | Pin Value in Sx/M3 |
|---|---|---|---|---|
| | Native | 0 | Depends on Intel® CSME power package and power source (Note 1) | 0 |
| GPP_A02 | IN | High-Z | High-Z | High-Z |
| OUT | Depends on GPP_A02 output data value | Depends on GPP_A02 output data value | Depends on GPP_A02 output data value |
| Reset Type (Note) | SPDA Value |
|---|---|
| Power-cycle Reset | 0 |
| Global Reset | 0 |
| Straight to S5 | Processor initially drive ‘0’ and then drive per Intel® CSME power policy configuration. |
| | |
RTCRST# and SRTCRST#
RTCRST# is used to reset processor registers in the RTC Well to their default value. If a jumper is used on this pin, it should only be pulled low when system is in the G3 state and then replaced to the default jumper position. Upon booting, BIOS should recognize that RTCRST# was asserted and clear internal processor registers accordingly. It is imperative that this signal not be pulled low in the S0 to S5 states.
SRTCRST# is used to reset portions of the Intel® Converged Security and Management Engine and should not be connected to a jumper or button on the platform. The only time this signal gets asserted (driven low in combination with RTCRST#) should be when the coin cell battery is removed or not installed and the platform is in the G3 state. Pulling this signal low independently (without RTCRST# also being driven low) may cause the platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that SRTCRST# not be pulled low in the S0 to S5 states.