DDR0_​DQ[3:0][7:0]

DDR1_​DQ[3:0][7:0]

DDR2_​DQ[3:0][7:0]

DDR3_​DQ[3:0][7:0]

Data Buses: Data signals interface to the SDRAM data buses.

Example: DDR0_​DQ2[5] refers to DDR channel 0, Byte 2, Bit 5.

I/O

DDR5

SE

H/U Processor

DDR0_​DQSP[3:0]

DDR0_​DQSN[3:0]

DDR1_​DQSP[3:0]

DDR1_​DQSN[3:0]

DDR2_​DQSP[3:0]

DDR2_​DQSN[3:0]

DDR3_​DQSP[3:0]

DDR3_​DQSN[3:0]

Data Strobes: Differential data strobe pairs. The data is captured at the crossing point of DQS during reading and write transactions.

Example: DDR0_​DQSP0 refers to DQSP of DDR channel 0, Byte 0.

I/O

DDR5

Diff

H/U Processor

DDR0_​CLK[1:0]_​P

DDR0_​CLK[1:0]_​N

DDR1_​CLK[1:0]_​P

DDR1_​CLK[1:0]_​N

DDR2_​CLK[1:0]_​P

DDR2_​CLK[1:0]_​N

DDR3_​CLK[1:0]_​P

DDR3_​CLK[1:0]_​N

SDRAM Differential Clock: Differential clocks signal pairs, pair per rank. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

O

DDR5

Diff

H/U Processor

DDR0_​CS[1:0]

DDR1_​CS[1:0]

DDR2_​CS[1:0]

DDR3_​CS[1:0]

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

The Chip select signal is Active Low.

O

DDR5

SE

H/U Processor

DDR0_​CA[12:0]

DDR1_​CA[12:0]

DDR2_​CA[12:0]

DDR3_​CA[12:0]

Command Address: These signals are used to provide the multiplexed command and address to the SDRAM.

O

DDR5

SE

H/U Processor

System Memory Resistance Compensation

H/U Processor

H/U Processor

DDR0_​DQ[1:0][7:0]

DDR1_​DQ[1:0][7:0]

DDR2_​DQ[1:0][7:0]

DDR3_​DQ[1:0][7:0]

DDR4_​DQ[1:0][7:0]

DDR5_​DQ[1:0][7:0]

DDR6_​DQ[1:0][7:0]

DDR7_​DQ[1:0][7:0]

Data Buses: Data signals interface to the SDRAM data buses.

Example: DDR0_​DQ[1][5] refers to DDR channel 0, Byte 1, Bit 5.

All Processor Series

DDR0_​DQSP[1:0]

DDR1_​DQSP[1:0]

DDR2_​DQSP[1:0]

DDR3_​DQSP[1:0]

DDR4_​DQSP[1:0]

DDR5_​DQSP[1:0]

DDR6_​DQSP[1:0]

DDR7_​DQSP[1:0]

DDR0_​DQSN[1:0]

DDR1_​DQSN[1:0]

DDR2_​DQSN[1:0]

DDR3_​DQSN[1:0]

DDR4_​DQSN[1:0]

DDR5_​DQSN[1:0]

DDR6_​DQSN[1:0]

DDR7_​DQSN[1:0]

All Processor Series

DDR0_​CLK_​N

DDR0_​CLK_​P

DDR1_​CLK_​N

DDR1_​CLK_​P

DDR2_​CLK_​N

DDR2_​CLK_​P

DDR3_​CLK_​N

DDR3_​CLK_​P

DDR4_​CLK_​N

DDR4_​CLK_​P

DDR5_​CLK_​N

DDR5_​CLK_​P

DDR6_​CLK_​N

DDR6_​CLK_​P

DDR7_​CLK_​N

DDR7_​CLK_​P

SDRAM Differential Clock:

Differential clocks signal pairs, pair per channel and package. The crossing of the positive edge and the negative edge of their complement are used to sample the command and control signals on the SDRAM.

All Processor Series

DDR0_​CS[1:0]

DDR1_​CS[1:0]

DDR2_​CS[1:0]

DDR3_​CS[1:0]

DDR4_​CS[1:0]

DDR5_​CS[1:0]

DDR6_​CS[1:0]

DDR7_​CS[1:0]

Chip Select: (1 per rank). These signals are used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

The Chip select signal is Active High.

All Processor Series

DDR0_​CA[6:0]

DDR1_​CA[6:0]

DDR2_​CA[6:0]

DDR3_​CA[6:0]

DDR4_​CA[6:0]

DDR5_​CA[6:0]

DDR6_​CA[6:0]

DDR7_​CA[6:0]

Command Address: These signals are used to provide the multiplexed command and address to the SDRAM.

All Processor Series

DDR0_​WCK_​P

DDR0_​WCK_​N

DDR1_​WCK_​P

DDR1_​WCK_​N

DDR2_​WCK_​P

DDR2_​WCK_​N

DDR3_​WCK_​P

DDR3_​WCK_​N

DDR4_​WCK_​P

DDR4_​WCK_​N

DDR5_​WCK_​P

DDR5_​WCK_​N

DDR6_​WCK_​P

DDR6_​WCK_​N

DDR7_​WCK_​P

DDR7_​WCK_​N

Write Clocks: WCK_​N and WCK_​P are differential clocks used for WRITE data capture and READ data output.

All Processor Series

System Memory Resistance Compensation

All Processor Series

All Processor Series