Intel® Core™ Ultra 200H and 200U Series Processors
Datasheet, Volume 1 of 2
Signal Description
| Signal Name | Type | Description |
|---|---|---|
| Intel® High Definition Audio Signals | ||
| O | Intel HD Audio Reset: Host H/W reset to internal and external codecs. | |
| O | Intel HD Audio Sync: 48 kHz fixed rate frame sync to the codecs. | |
| O | Intel HD Audio Bit Clock: Up to 24 MHz serial data clock generated by the Intel® HD Audio controller. | |
| O | Intel HD Audio Serial Data Out: Serial TDM data output to the codecs. The serial output is double-pumped for a bit rate of up to 48 Mb/s. | |
| I/O | Intel HD Audio Serial Data In 0: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. | |
| I/O | Intel HD Audio Serial Data In 1: Serial TDM data input from the two codec(s). The serial input is single-pumped for a bit rate of up to 24 Mb/s. These signals contain integrated Pull-down resistors, which are enabled while the primary well is powered. | |
| I2S / PCM Interface | ||
| I/O | I2S / PCM serial bit clock 0: Serial bit clock used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). | |
| I/O | I2S / PCM serial bit clock 1:Serial bit clock is used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). | |
| I/O | I2S / PCM serial bit clock 2: Serial bit clock is used to control the timing of a transfer. Can be generated internally (Host mode) or taken from an external source (Device mode). | |
| I/O | I2S / PCM serial frame indicator 0: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). | |
| I/O | I2S / PCM serial frame indicator 1: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). | |
| I/O | I2S / PCM serial frame indicator 1: This signal indicates the beginning and the end of a serialized data word. Can be generated internally (Host mode) or taken from an external source (Device mode). | |
| O | I2S / PCM transmit data (serial data out)0: Serial data out line. Sample length is a function of the selected serial data sample size. | |
| O | I2S / PCM transmit data (serial data out)1: Serial data out line. Sample length is a function of the selected serial data sample size. | |
| O | I2S / PCM transmit data (serial data out)1: Serial data out line. Sample length is a function of the selected serial data sample size. | |
| I | I2S / PCM receive data (serial data in)0: Serial data in line. Sample length is a function of the selected serial data sample size. | |
| I | I2S / PCM receive data (serial data in)1: Serial data in line. Sample length is a function of the selected serial data sample size. | |
| I | I2S / PCM receive data (serial data in)1: Serial data in line. Sample length is a function of the selected serial data sample size. | |
| O | I2S / PCM Host reference clock 0: This signal is the host reference clock that connects to an audio codec. | |
| DMIC Interface | ||
or | O | Digital Mic Clock A0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance A) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance A) should be used. |
or | O | Digital Mic Clock A1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance A) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance A) should be used. |
or | O | Digital Mic Clock B0:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance B) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance B) can be disconnected. |
or | O | Digital Mic Clock B1:Serial data clock generated by the HD Audio controller. The clock output frequency is up to 4.8 MHz. Duplication for clock pin (instance B) in case platform wanted to separate clock connection for left channel mic vs right channel mic. For the case of sharing single clock connection to both left and right channel mics, clock pin (instance B) can be disconnected. |
or | I | Digital Mic Data:Serial data input from the digital mic. |
or | I | Digital Mic Data:Serial data input from the digital mic. |
| SoundWire Interface | ||
| I/O | SoundWire Clock: Serial bit clock used to control the timing of a transfer. | |
| I/O | SoundWire Data: Serialized data line containing framing and data being transmitted/received. | |
| I/O | SoundWire Clock: Serial bit clock used to control the timing of a transfer. SoundWire Data: Serialized data line containing framing and data being transmitted/received. | |
| I/O | SoundWire Data: Serialized data line containing framing and data being transmitted/received. | |
| I/O | SoundWire Clock: Serial bit clock used to control the timing of a transfer. SoundWire Data: Serialized data line containing framing and data being transmitted / received. | |
| I/O | SoundWire Data: Serialized data line containing framing and data being transmitted / received. | |
| I/O | SoundWire Clock: Serial bit clock used to control the timing of a transfer. | |
| I/O | SoundWire Data: Serialized data line containing framing and data being transmitted / received. | |
| SNDW_RCOMP | A | SoundWire Resistor compensation. |