DDR5 Signal DC Specifications

Eagle Stream Platform

Data Sheet

ID	Date	Version	Classification
814095	04/04/2025	001	Public

For the next table, use Signal Group Table: Signal Groups to identify which signals belong to each group.

Symbol	Parameter	Min.	Nom.	Max.	Units	Notes₁
IIL	Input Leakage Current	-1.4		+1.4	mA	9
Data Signals
R ON	DDR5 Data Buffer On Resistance	30	37.5	45	Ω	6
Data ODT	On Die Termination	40	50	60	Ω	8
Reference Clock and Command Signals
VOL	Output Low Voltage		Vol = (Ron / (Ron + RVDD_TERM)) ×VCCD		V	2, 7
VOH	Output High Voltage		VCCD		V	2, 5, 7, 11
Data Signals
VOL	Output Low Voltage		Vol = (Ron / (Ron + RVDD_TERM)) ×VCCD			2,10
VOH	Output High Voltage		VCCD			2
Reference Clock Signal
R ON	DDR5 Clock Buffer On Resistance	28	35	42	Ω	6
Command Signals
R ON	DDR5 Command Buffer On Resistance	28	35	42	Ω	6
VOL_CMOS1.1V	Output Low Voltage, Signals DDR_RESET_C{01/23}_N			0.55×V_CCD	V	1, 2
V OH_CMOS1.1V	Output High Voltage, Signals DDR_RESET_C{01/23}_N	0.95×V_CCD			V	1, 2
Control Signals
R ON	DDR5 Control Buffer On Resistance	28	35	42	Ω	6
DDR5 Miscellaneous Signals
DRAM{01/23/45/67}_PWR_OK
R ON	DDR5 Reset Buffer On Resistance	35	45	55	Ω	6
VIL	Input Low Voltage		0.3 × VCCD		mV	2, 3
VIH	Input High Voltage		0.7 × VCCD		mV	2, 4, 5
ALERT_N
VIL	Input Low Voltage	Vref -100		Vref -80	mV	3
VIH	Input High Voltage	Vref +80		Vref +100	mV	4
ODT	On Die Termination	56	70	84	Ω
*Notes:* Unless otherwise noted, all specifications in this table apply to all processor frequencies. The voltage rail VCCD which will be set to 1.1V nominal depending on the voltage of all DIMMs connected to the processor. VIL is the maximum voltage level at a receiving agent that will be interpreted as a logical low value. VIH is the minimum voltage level at a receiving agent that will be interpreted as a logical high value. VIH and VOH may experience excursions above VCCD. However, input signal drivers must comply with the signal quality specifications. Refer to Section 2.11 Signal Quality. This is the pull down driver resistance. Refer to processor signal integrity models for I/V characteristics. Reset drive does not have a termination. RVTT_TERM is the termination on the DIMM and not controlled by the processor. Refer to the applicable DIMM datasheet. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs. Input leakage current is specified for all DDR5 signals. Vol = Ron × [VCCD/(Ron + Rtt_Eff)], where Rtt_Eff is the effective pull-up resistance of all DIMMs in the system, including ODTs and series resistors on the DIMMs. The VCCD value refers VCCD_HV power supply pins.