Eagle Stream Platform
Data Sheet
Processor Asynchronous Miscellaneous I/O AC Specifications
| Parameter | Min. | Max. | Unit | Figure | Notes1 |
|---|---|---|---|---|---|
| T2: PROCHOT_N Input Pulse Width Low. | 500 | μs | Figure: JTAG/Tap and Processor Sideband Signals High/Low Pulse Widths and Rise/Fall Times | ||
| T1: PROCHOT_N Input Pulse Width High. | 5 | μs | |||
| T2: PROCHOT_N Output Pulse Width Low. | 500 | μs | |||
| T1: PROCHOT_N Output Pulse Width High. | 500 | μs | |||
| Ts: PROCHOT_N Setup Time. | 1 | μs | Figure: PROCHOT_N Setup and Hold Timing Waveforms | ||
| Th: PROCHOT_N Hold Time. | TBD | μs | |||
| T3: PROCHOT_N Rise Time. | 80 | ns | 10 | ||
| T4: PROCHOT_N Fall Time. | 80 | ns | 10 | ||
| T2: RESET_N Input Pulse Width Low. | 3.5 | ms | |||
| T1: RESET_N Input Pulse Width High. | 4 | BCLK0 | |||
| T3, T4: RESET_N Rise Time (VIL to VIH) / Fall Time (VIH to VIL). | 15 | ns | |||
| T7: FRB Cold Boot: RESET_N de- assertion to PROCDIS_N de- assertion. | 1 | μs | Figure: Fault Resilient Booting (FRB) Timing Requirements | ||
| T8: FRB Warm Boot: PROCDIS_N assertion to RESET_N assertion. | 1 | μs | |||
| T9: FRB Warm Boot: RESET_N de- assertion to PROCDIS_N de- assertion. | 1 | μs | |||
| T2: CATERR_N Input Pulse Width Low. | 3 | BCLK0 | 6 | ||
| T1: CATERR_N Input Pulse Width High. | 3 | BCLK0 | |||
| T2: CATERR_N Output Pulse Width Low. | 16 | BCLK0 | |||
| T3: CATERR_N Rise Time. | 80 | ns | 10 | ||
| T4: CATERR_N Fall Time. | 80 | ns | 10 | ||
| T10: THERMTRIP_N assertion until VCCIN/VCCINFAON/VCCD removed. | 500 | ms | Figure: THERMTRIP_N Assertion Until VCCIN, VCCD, VCCVNN and VCCVNN Removal | 6 | |
| MEM_HOT_C{01/23}_N Output Pulse Width Low and High. | 1 | DCLK | 2, 3 | ||
| MEM_HOT_C{01/23}_N Input Pulse Width Low. | >MH_SENSE_ PERIOD | <=MH_SENSE_ PERIOD | μs | Figure: MEM_HOT_C(012/345)_N Event Assertion Waveform | 4 |
| T3:MEM_HOT_C{01/23}_N Rise Time. | 80 | ns | Figure: JTAG/Tap and Processor Sideband Signals High/Low Pulse Widths and Rise/Fall Times | 10 | |
| T4:MEM_HOT_C{01/23}_N Fall Time. | 80 | ns | 10 | ||
| T3:PWRGOOD Input Signals Rise Time T4:PWRGOOD Input Signals Fall Time. | 50 | ns | 5 | ||
| T11: BCLK0 stable to PWRGOOD assertion. | 10 | BCLK0 | Table: Voltage Sequence Timing Requirements | ||
| T12: PWRGOOD assertion to RESET_N de-assertion. | 3.5 | ms | 7, 8 | ||
| T13: TSetup:Power-On Configuration Setup Time to PWRGOOD assertion, Signals: BMCINIT, TXT_PLTEN, FRMAGENT, TXT_AGENT, SAFE_MODE_BOOT, SOCKET_ID[1:0]. | 1 | μs | 6 | ||
| T14: THold:Power-On Configuration Hold Time, Signals: BMCINIT, TXT_PLTEN, FRMAGENT, TXT_AGENT, SAFE_MODE_BOOT, SOCKET_ID[1:0]. | TBD | μs | 6 | ||
| T15: VCCINFAON stable to PWRGOOD assertion. | 1 | ms | |||
| PROCDIS Pulse Width. | 50 | ns | |||
| PROCDIS Setup Time to PWRGOOD. | 0 | ns | |||
| PROCDIS Setup Time to RESET_N assertion edge. | 0 | ns | |||
| PROCDIS Hold Time to PWRGOOD. | 10 | ms | |||
| PROCID Hold Time to RESET_N assertion edge. | 1 | ms | |||
| T3: NMI Input Signals Rise Time. | 80 | ns | Table: Voltage Sequence Timing Requirements | 10 |
- Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- DCLK is DDR{0/1/2/3/4/5/6/7}_CLK_DN/DP[3:0]. DCLK is relative to the MH_IN_SENSE_ASSERT range, but the whole MEM_HOT_C(012/345)_N output assertion time is based on the MEM_HOT_C(012/345)_N event assertion, Figure: MEM_HOT_C(012/345)_N Event Assertion Waveform
- Maximum High pulse width is constant High when there are no MEM_HOT_C(012/345)_N events, and the MH_SENSE_EN=0.
- MH_SENSE_PERIOD is the MEM_HOT_C(012/345)_N sense period and guarantees external assertion detection, see the
4th Gen Intel® Xeon® Scalable Processor, Codename Sapphire Rapids, Sapphire Rapids EE, Emerald Rapids Processor, or Eagle Stream Platform Register Specification and theEagle Stream Platform BIOS Writer's Guide . This is the configurable sense period and sense assertion time. When sense assertion time is set to zero, and the processor is asserting MEM_HOT_C(012/345)_N it will ignore externally asserted MEM_HOT_C{01/23}_N. - Sense period: 50 μs, 100 μs, 200 μs, or 400 μs. This timing value is the one measured from ViL to ViH.
- Sense assertion time: 0, 1 μs, 1.5 μs, 2 μs, 2.5 μs, 3 μs, or 3.5 μs.
- Tpwrgood_fall and Tpwrgood_rise are measured: 0.3×VCCINFAON to 0.7×VCCINFAON.
- These signals are sampled after PWRGOOD assertion.
- To meet TSC (Time Stamp Counter) multi-socket sampling, PWRGOOD must arrive to all processors within 1 BCLK{0/1} and the BCLK{0/1} skew between the sockets should be less than one-half (1/2) BCLK{0/1} cycle. For details on platform implementation, see the appropriate Platform Design Guide (PDG).
- This timing value is the one measured from ViL - 50 mV to ViH + 50 mV.
JTAG/Tap and Processor Sideband Signals High/Low Pulse Widths and Rise/Fall Times
PROCHOT_N Setup and Hold Timing Waveforms
Fault Resilient Booting (FRB) Timing Requirements
THERMTRIP_N Assertion Until VCCIN, VCCD, VCCVNN and VCCVNN Removal
| See the |