SBLINK AC Specifications
This section describes the DC Specifications for the SBLINK.
| Symbol | Parameter | Min. | Max. | Units | Figure | Notes2 |
|---|
| Tco | CLK to Data Delay PMDOWN_PCH | 7.32 | 23.41 | ns | | 1 |
| CLK to Data Delay PMDOWN[6:0] (1S/2S CPU) | 7.32 | 23.41 | ns | | 1,3 |
| CLK to Data Delay PMDOWN[6:0](4S/8S CPU) | 5.00 | 15.70 | ns | | 1,4 |
| Tsu | Setup Time PMSYNC[6:0]/PMSYNC_PCH | 1.86 | - | ns | | 1 |
| Thd | Hold Time PMSYNC[6:0]/PMSYNC_PCH | 2.19 | - | ns | | 1 |
| Input SR | Slew Rate PMSYNC[6:0]/PMSYNC_PCH | 40 | 1000 | mV/ns | | 5 |
| Notes: -
The XTAL_CLK measurement threshold should be 150 mV on rising edge of the differential waveform. - Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- Timing applies to CPU QDFs/S-Specs that only support one and two socket operation.
- Timing applies to CPU QDFs/S-Specs that support four or greater socket operation.
- Parameter to be measured between VIL-VIH.
|
SBLINK Setup and Hold timing Waveforms