System Reference Clocks (BCLK{0/1/2/3}_DP, BCLK{0/1/2/3}_DN)

The processor Core, processor Uncore, Intel® UPI, PCI Express and DDR5 memory interface frequencies are generated from BCLK{0/1/2/3}_​DP and BCLK{0/1/2/3}_​DN signals. There is no direct link between core frequency and Intel® UPI link frequency (for example, no core frequency to Intel® UPI multiplier). The processor maximum core frequency, Intel® UPI link frequency and DDR memory frequency are set during manufacturing.

Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK{0/1/2/3}_​DP, BCLK{0/1/2/3}_​DN input. DC specifications for the BCLK{0/1/2/3}_​DP, BCLK{0/1/2/3}_​DN inputs are provided in Processor Asynchronous Miscellaneous I/O DC Specifications.

These specifications must be met while also meeting the associated signal quality specifications outlined in Signal Quality.

Details regarding BCLK{0/1/2/3}_​DP, BCLK{0/1/2/3}_​DN driver specifications are provided in the CK404 Clock Synthesizer/Driver Specification.