Eagle Stream Platform
Data Sheet
Signal Group Summary
Signals are grouped by buffer type and similar characteristics as listed in the following table. The buffer type indicates which signaling technology and specifications apply to the signals.
| Signal | Description |
|---|---|
| Analog | Analog reference or output. May be used as a threshold voltage or for buffer compensation. |
| Asynchronous | Signal has no timing relationship with any system reference clock. |
| CMOS | CMOS Output buffers: 1.05V tolerant / CMOS Input buffers. |
| DDR5 | CMOS Output buffers: 1.1V tolerant. |
| DMI3 | Direct Media Interface Gen 3 signals. Non legacy DMI ports are compatible with PCI Express 4.0 Signaling Base and CEM Specifications. |
| Intel® UPI | Nominal voltage: 1.0V. |
| Open Drain | Open Drain buffers: 1.05V tolerant. |
| PCI Express | PCIe 5.0: These signals are compatible with PCI Express 5.0 Signaling Base and CEM Specifications and are AC coupled. |
| Reference | Voltage reference signal. |
| SSTL | Source Series Terminated Logic (JEDEC SSTL_15). |
| Differential/Single Ended | Buffer Type | Signal |
|---|---|---|
| DDR5 Reference Clocks | ||
| Differential | SSTL Output | DDR{0/1/2/3/4/5/6/7}_CLK_D[N/P] [1:0] |
| DDR5 Command Signals | ||
| Single-ended | SSTL Output | DDR{0/1/2/3/4/5/6/7}_SA_CA[6:0] DDR{0/1/2/3/4/5/6/7}_SB_CA[6:0] DDR{0/1/2/3/4/5/6/7}_SA_PAR DDR{0/1/2/3/4/5/6/7}_SB_PAR |
| DDR5 Control Signals | ||
| Single-ended | SSTL Output | DDR{0/1/2/3/4/5/6/7}_SA_CS_N[3:0] DDR{0/1/2/3/4/5/6/7}_SB_CS_N[3:0] |
| DDR5 Data Signals | ||
| Differential | SSTL Input/Output | DDR{0/1/2/3/4/5/6/7}_SA_DQS_D[N/P] [9:0] DDR{0/1/2/3/4/5/6/7}_SB_DQS_D[N/P] [9:0]
|
| Single-ended | SSTL Input/Output | DDR{0/1/2/3/4/5/6/7}_SA_DQ[31:0] DDR{0/1/2/3/4/5/6/7}_SB_DQ[31:0] DDR{0/1/2/3/4/5/6/7}_SA_ECC[7:0] DDR{0/1/2/3/4/5/6/7}_SB_ECC[7:0] |
| DDR5 Miscellaneous Signals | ||
| Single-ended | SSTL Input | DDR{0/1/2/3/4/5/6/7}_ALERT_N |
| CMOS Input Note: Input voltage from platform cannot exceed 1.2V max. | DDR{01,23,45,67}_DRAM_PWR_OK DDR{0/1/2/3/4/5/6/7}_A_RSP[1:0] DDR{0/1/2/3/4/5/6/7}_B_RSP[1:0] | |
| CMOS 1.1V Output | DDR{01,23,45,67}_RESET_N | |
| Open Drain Output / CMOS Input | DDR[0123,4567]_SPDSCL DDR[0123,4567]_SPDSDA | |
| PCI Express Port 0, 1, 2, 3, and 4 Signals | ||
| Differential | PCI Express Input | PE{4:0}_RX_DN/DP[15:0] |
| Differential | PCI Express Output | PE{4:0}_TX_DN/DP[15:0] |
| PCI Express Miscellaneous Signals | ||
| Single-ended | Open Drain Output | CXPSMBBUSSCL |
| Single-ended | Open Drain Output/CMOS Input | CXPSMBUSSDA |
| Single-ended | Open Drain Input | CXPSMBUS_ALERT_N |
| DMI3/PCI Express* Signals | ||
| Differential | DMI3 Input | DMI_RX_D[N/P][7:0] |
| DMI3 Output | DMI_TX_D[N/P][7:0] | |
| Single-ended | DMI Miscellaneous | DMIMODE_OVERRIDE |
| Intel® UPI Signals | ||
| Differential | Intel® UPI Input Output | UPI{3:0}_RX/TX_DN/DP[23:0] |
| Platform Environmental Control Interface (PECI) | ||
| Single-ended | PECI Input/Output | PECI |
| System Reference Clock (BCLK(0/1/2/3), XTAL_CLK) | ||
| Differential | Differential Input / CMOS Output | BCLK(0/1/2/3)_D[N/P] |
| Differential | Differential Input/ CMOS Output | XTAL_CLK |
| JTAG and TAP Signals | ||
| Single ended | CMOS Input | TCK,TDI,TMS, PREQ_N |
| Open Drain Output | TDO, PRDY_N | |
| Serial VID Interface (SVID) Signals | ||
| Single ended | CMOS Input | SVIDALERT{1/0}_N |
| Open Drain Output / CMOS Input | SVIDDATA [1:0] | |
| Open Drain Output | SVIDCLK [1:0] | |
| Processor Sideband Link | ||
| Single ended | PMSYNC[6:0], PMDOWN[6:0], PMDOWN_PCH, PMSYNC_PCH | |
| Processor Asynchronous Sideband Signals | ||
| Single ended | CMOS Input | BIST_ENABLE, BMCINIT, LEGACY_SKT, NMI, TEST_PU_DA52, SOCKET_ID[2:0] FRMAGENT, PWRGOOD, RESET_N, SAFE_MODE_BOOT, TXT_AGENT TXT_PLTEN, PROCHOT_N |
| Open Drain Output / CMOS Input | CATERR_N, MEMHOT_OUT_N, MEMHOT_IN_N, PMFAST_WAKE_N | |
| Open Drain Output | ERROR_N[2:0], THERMTRIP_N | |
| Not connected to Silicon | SKTOCC_N, PKG_ID[2:0], PROC_ID[1:0] | |
| Power/Other Signals | ||
| Power / Ground | VCCIN, VCCINFAON, VCCFA_EHV, VCCFA_EHV_FIVRA, VCCD_HV, VCCVNN, VPP_HBM, VPP_HBM[4:1],VCC_3P3_AUX[1:0] and VSS | |
| Sense Points | VCCINFAON_SENSE VSS_VCCINFAON_SENSE, VCCFA_EHV_SENSE VSS_VCCFA_EHV_SENSE, VCCFA_EHV_FIVRA_SENSE VSS_VCCFA_EHV_FIVRA_SENSE, VCCD_HV_SENSE VSS_VCCD_HV_SENSE, VCCIN_SENSE, VSS_VCCIN_SENSE | |
| Notes:
| ||
| Signal Name | Pull Up/Pull Down | Rail | Value | Units | Notes |
|---|---|---|---|---|---|
| BIST_ENABLE | Pull Up | VCCVNN | 3K-8K | ohm | - |
| BMCINIT | Pull Down | VSS | 3K-8K | ohm | - |
| DMIMODE_OVERRIDE | Pull Up | VCCVNN | 3K-8K | ohm | - |
| FBRK_N | Pull Up | VCCVNN | 3K-8K | ohm | - |
| FRMAGENT | Pull Down | VSS | 3K-8K | ohm | - |
| LEGACY_SKT | Pull Down | VSS | 3K-8K | ohm | - |
| MEMHOT_IN_N | Pull Up | VCCVNN | 3K-8K | ohm | - |
| NMI | Pull Down | VSS | 3K-8K | ohm | - |
| PARTITION_ID[1:0] | Pull Down | VSS | 3K-8K | ohm | - |
| PECI | Pull Down | VSS | 3K-8K | ohm | - |
| PMDDOWN[6:0] | Pull Down | VSS | 3K-8K | ohm | - |
| PMAX_TRIGGER_IO | Pull Down | VSS | 3K-8K | ohm | - |
| PMFAST_WAKE_N | Pull Up | VCCVNN | 3K-8K | ohm | - |
| PMSYNC[6:0] | Pull Down | VSS | 3K-8K | ohm | - |
| TEST_PU_DA52 | Pull Up | VCCVNN | 3K-8K | ohm | - |
| PROCHOT_N | Pull Up | VCCVNN | 3K-8K | ohm | - |
| SAFE_MODE_BOOT | Pull Down | VSS | 3K-8K | ohm | - |
| SOCKET_ID[2:0] | Pull Down | VSS | 3K-8K | ohm | - |
| TAP_ODT_EN | Pull Down | VSS | 3K-8K | ohm | - |
| TCK | Pull Down | VSS | 3K-8K | ohm | - |
| TDI | Pull Up | VCCVNN | 3K-8K | ohm | - |
| TMS | Pull Up | VCCVNN | 3K-8K | ohm | - |
| TXT_AGENT | Pull Down | VSS | 3K-8K | ohm | - |
| TXT_PLTEN | Pull Up | VCCVNN | 3K-8K | ohm | - |