PECI DC Specifications

Symbol	Definition and Conditions	Min.	Max.	Units	Figure	Notes₁
VIn	Input Voltage Range	-0.15	0.15 + VCCINFAON	V		1
VHysteresis	Hysteresis	0.1×VCCINFAON		V
VIL Input Low Voltage	maximum voltage for low input	-	0.35×VCCINFAON	V
VIH Input High Voltage	minimum voltage for high input	0.65×VCCINFAON	-	V
VN	Negative-edge threshold voltage	0.275×VCCINFAON	0.500×VCCINFAON	V	Figure: Input Device Hysteresis	2
VP	Positive-edge threshold voltage	0.550×VCCINFAON	0.725×VCCINFAON	V	Figure: Input Device Hysteresis	2
I Source	Pullup Resistance (VOH = 0.75×VCCINFAON)	-6.00	-	mA
ILeak+	High impedance state leakage to VCCINFAON (Vleak = VOL)	±10	±320	μA		3, 4
RPU	Pull up resistance	13.4	26.6	ohm
CBus	Bus capacitance per node		10	pF		5
VNoise	Signal noise immunity above 300 MHz	0.100×VCCINFAON		Vp-p
	Output Edge Rate (50Ω to VSS, between VIL and VIH)	5	15	V/ns
*Notes:* The input voltage range specifies an overshoot/undershoot that applies only to the PECI data signal and not to the VTT reference itself. It is expected that the PECI driver will take into account, the variance in the receiver input thresholds and consequently, be able to drive its output within safe limits (-0.150 V to 275×VCCINFAON for the low level and 725×VCCINFAON to VCCINFAON+0.150V for the high level). VCCINFAON nominal levels will vary between processor families. All PECI devices will operate at the VCCINFAON level determined by the processor installed in the system. The leakage specification applies to powered devices on the PECI bus. Consider Min value to be at VIL/VIH while max value is at VCCINFAON. Excessive capacitive loading on the PECI line may slow down the signal rise/fall times and consequently limit the maximum bit rate at which the interface can operate.

System Reference Clock (BCLK{0/1/2/3}) DC Specifications

DDR5 Signal DC Specifications System Reference Clock (BCLK{0/1/2/3}) DC Specifications