| XTAL_CLK Clock Frequency | Differential | 24.9975 | 25 | 25.0025 | MHz | | 2, 7, 8 |
| XTAL_CLK Period | Differential | 39.996 | 40 | 40.004 | ns | | 2, 7, 8 |
| XTAL_CLK Edge Rate | Differential | 1.0 | | 4.0 | V/ns | Figure: BCLK(0/1/2/3) Differential Clock Measurement Points for Edge Rate | 4, 7, 9, 10 |
| XTAL_CLK Dutycycle | Differential | 45 | | 55 | % | Figure: BCLK(0/1/2/3) Differential Clock Measurement Points for Duty Cycle and Period | 7, 9 |
| XTAL_CLK cycle to cycle jitter | Differential | | | |1.3| | ns | | 3, 7 |
| VRB | Differential | -100 | | 100 | mV | Figure: BCLK(0/1/2/3) Differential Clock Measurement Point for Ringback | 5, 7, 9 |
| TStable | Differential | 500 | | | ps | 6, 7, 9 |
| Notes: - Unless otherwise noted, all specifications in this table apply to all processor frequencies.
- Average Period.
- This is absolute cycle to cycle jitter.
- Edge Rate (V/ns) is calculated as 250 mV divided by the rise or fall times measured using the thresholds in Figure: BCLK(0/1/2/3) Differential Clock Measurement Points for Edge Rate.
- Measurement Taken from differential waveform.
- TStable is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges, before it is allowed to droop back into the VRB ±100 mV range. See Figure: BCLK(0/1/2/3) Differential Clock Measurement Point for Ringback.
- Specifications can be validated at the pin.
- XTAL_CLK does not support spread spectrum clocking (SSC). Measure with a frequency counter.
- BCLK Figures are applicable to XTAL_CLK.
- Measured with a CPU in the socket to get loading effects from multiple dice. Sapphire Rapids XCC provides maximum loading for min spec measurement. The dice bumps require edge rates of 0.4 V/ns minimum and 4.0 V/ns maximum.
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