Serial VID (SVID) Interface AC Timing Specifications

Symbol	Parameter	Min.	Nom.	Max.	Units	Figure	Notes
	SVIDCLK Frequency (VCLK).		25		MHz	Figure: Serial VID Interface (SVID) Signals Clock Timings	1
TPeriod	Absolute Minimum SVIDCLK Period.	(1/VCLK) - 5%	(1/VCLK)	(1/VCLK) + 5%	ns		1
THigh/Low	SVIDCLK High and Low Time.	(1/VCLK)/2 - 20%	(1/VCLK)/2	(1/VCLK)/2 + 20%	ns		1, 3, 4
Tco	SVIDDATA Output Delay from SVIDCLK.	-1		1	ns		1, 2, 4
TS	SVIDDATA Input Setup Time.	1			ns		1
TH	SVIDDATA Input Hold Time.	5			ns		1, 2
*Notes:* Unless otherwise noted, all specifications in this table apply to all processor frequencies. Referenced to the rising edge of SVIDCLK at 0.5×VCCINFAON. THigh is measured with respect to 0.7×VCCINFAON. T_Lowtime is measured with respect to 0.3×VCCINFAON. Value obtained through test bench with 50Ω pull up to VCCINFAON.

JTAG and TAP Signal AC Specifications Processor Asynchronous Miscellaneous I/O AC Specifications